Loading target-sparc/cpu.h +3 −2 Original line number Diff line number Diff line Loading @@ -415,14 +415,15 @@ struct CPUSPARCState { #if !defined(TARGET_SPARC64) int psref; /* enable fpu */ #endif target_ulong version; int interrupt_index; uint32_t nwindows; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[MAX_NWINDOWS * 16 + 8]; CPU_COMMON target_ulong version; uint32_t nwindows; /* MMU regs */ #if defined(TARGET_SPARC64) uint64_t lsu; Loading target-sparc/cpu_init.c +1 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,7 @@ void cpu_state_reset(CPUSPARCState *env) log_cpu_state(env, 0); } memset(env, 0, offsetof(CPUSPARCState, breakpoints)); tlb_flush(env, 1); env->cwp = 0; #ifndef TARGET_SPARC64 Loading Loading
target-sparc/cpu.h +3 −2 Original line number Diff line number Diff line Loading @@ -415,14 +415,15 @@ struct CPUSPARCState { #if !defined(TARGET_SPARC64) int psref; /* enable fpu */ #endif target_ulong version; int interrupt_index; uint32_t nwindows; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[MAX_NWINDOWS * 16 + 8]; CPU_COMMON target_ulong version; uint32_t nwindows; /* MMU regs */ #if defined(TARGET_SPARC64) uint64_t lsu; Loading
target-sparc/cpu_init.c +1 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,7 @@ void cpu_state_reset(CPUSPARCState *env) log_cpu_state(env, 0); } memset(env, 0, offsetof(CPUSPARCState, breakpoints)); tlb_flush(env, 1); env->cwp = 0; #ifndef TARGET_SPARC64 Loading