Commit 89494462 authored by Bin Meng's avatar Bin Meng Committed by Alistair Francis
Browse files

hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions 



This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.

Signed-off-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 8f8c6c1a

hw/riscv/opentitan.c

+14 −15
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static const struct MemmapEntry { 
    [IBEX_PADCTRL] =        {  0x40160000,  0x10000 }

};



static void riscv_opentitan_init(MachineState *machine)

static void opentitan_board_init(MachineState *machine)

{

    const struct MemmapEntry *memmap = ibex_memmap;

    OpenTitanState *s = g_new0(OpenTitanState, 1);
@@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine) 
    memory_region_add_subregion(sys_mem,

        memmap[IBEX_RAM].base, main_mem);





    if (machine->firmware) {

        riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);

    }
@@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine) 
    }

}



static void riscv_opentitan_machine_init(MachineClass *mc)

static void opentitan_machine_init(MachineClass *mc)

{

    mc->desc = "RISC-V Board compatible with OpenTitan";

    mc->init = riscv_opentitan_init;

    mc->init = opentitan_board_init;

    mc->max_cpus = 1;

    mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;

}



DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)

DEFINE_MACHINE("opentitan", opentitan_machine_init)



static void riscv_lowrisc_ibex_soc_init(Object *obj)

static void lowrisc_ibex_soc_init(Object *obj)

{

    LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
@@ -101,7 +100,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) 
    object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);

}



static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)

static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)

{

    const struct MemmapEntry *memmap = ibex_memmap;

    MachineState *ms = MACHINE(qdev_get_machine());
@@ -186,26 +185,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 
        memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);

}



static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = riscv_lowrisc_ibex_soc_realize;

    dc->realize = lowrisc_ibex_soc_realize;

    /* Reason: Uses serial_hds in realize function, thus can't be used twice */

    dc->user_creatable = false;

}



static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {

static const TypeInfo lowrisc_ibex_soc_type_info = {

    .name = TYPE_RISCV_IBEX_SOC,

    .parent = TYPE_DEVICE,

    .instance_size = sizeof(LowRISCIbexSoCState),

    .instance_init = riscv_lowrisc_ibex_soc_init,

    .class_init = riscv_lowrisc_ibex_soc_class_init,

    .instance_init = lowrisc_ibex_soc_init,

    .class_init = lowrisc_ibex_soc_class_init,

};



static void riscv_lowrisc_ibex_soc_register_types(void)

static void lowrisc_ibex_soc_register_types(void)

{

    type_register_static(&riscv_lowrisc_ibex_soc_type_info);

    type_register_static(&lowrisc_ibex_soc_type_info);

}



type_init(riscv_lowrisc_ibex_soc_register_types)
 
type_init(lowrisc_ibex_soc_register_types)