Commit 88536935 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David Gibson
Browse files

ppc: Update LPCR definitions 



Includes all the bits up to ISA 2.07

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 8eeb330c

target-ppc/cpu.h

+13 −3
Original line number Diff line number Diff line
@@ -377,12 +377,16 @@ struct ppc_slb_t { 
#define LPCR_VPM1         (1ull << (63 - 1))

#define LPCR_ISL          (1ull << (63 - 2))

#define LPCR_KBV          (1ull << (63 - 3))

#define LPCR_DPFD_SHIFT   (63 - 11)

#define LPCR_DPFD         (0x3ull << LPCR_DPFD_SHIFT)

#define LPCR_VRMASD_SHIFT (63 - 16)

#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)

#define LPCR_RMLS_SHIFT   (63 - 37)

#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)

#define LPCR_ILE          (1ull << (63 - 38))

#define LPCR_MER          (1ull << (63 - 52))

#define LPCR_LPES0        (1ull << (63 - 60))

#define LPCR_LPES1        (1ull << (63 - 61))

#define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */

#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)

#define LPCR_ONL          (1ull << (63 - 45))

#define LPCR_P7_PECE0     (1ull << (63 - 49))

#define LPCR_P7_PECE1     (1ull << (63 - 50))

#define LPCR_P7_PECE2     (1ull << (63 - 51))
@@ -391,6 +395,12 @@ struct ppc_slb_t { 
#define LPCR_P8_PECE2     (1ull << (63 - 49))

#define LPCR_P8_PECE3     (1ull << (63 - 50))

#define LPCR_P8_PECE4     (1ull << (63 - 51))

#define LPCR_MER          (1ull << (63 - 52))

#define LPCR_TC           (1ull << (63 - 54))

#define LPCR_LPES0        (1ull << (63 - 60))

#define LPCR_LPES1        (1ull << (63 - 61))

#define LPCR_RMI          (1ull << (63 - 62))

#define LPCR_HDICE        (1ull << (63 - 63))



#define msr_sf   ((env->msr >> MSR_SF)   & 1)

#define msr_isf  ((env->msr >> MSR_ISF)  & 1)