Commit 884f17c2 authored by Alex Bligh's avatar Alex Bligh Committed by Stefan Hajnoczi
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aio / timers: Convert rtc_clock to be a QEMUClockType 



Convert rtc_clock to be a QEMUClockType

Move rtc_clock users to use the new API

Signed-off-by: default avatarAlex Bligh <alex@alex.org.uk>
Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
parent 7bf8fbde

hw/arm/omap1.c

+2 −2
Original line number Diff line number Diff line
@@ -2894,7 +2894,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) 
    s->pm_am = 0;

    s->auto_comp = 0;

    s->round = 0;

    s->tick = qemu_get_clock_ms(rtc_clock);

    s->tick = qemu_clock_get_ms(rtc_clock);

    memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));

    s->alarm_tm.tm_mday = 0x01;

    s->status = 1 << 7;
@@ -2915,7 +2915,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, 


    s->irq = timerirq;

    s->alarm = alarmirq;

    s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s);

    s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);



    omap_rtc_reset(s);

hw/arm/pxa2xx.c

+19 −16
Original line number Diff line number Diff line
@@ -842,7 +842,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) 


static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)

{

    int64_t rt = qemu_get_clock_ms(rtc_clock);

    int64_t rt = qemu_clock_get_ms(rtc_clock);

    s->last_rcnr += ((rt - s->last_hz) << 15) /

            (1000 * ((s->rttr & 0xffff) + 1));

    s->last_rdcr += ((rt - s->last_hz) << 15) /
@@ -852,7 +852,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) 


static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)

{

    int64_t rt = qemu_get_clock_ms(rtc_clock);

    int64_t rt = qemu_clock_get_ms(rtc_clock);

    if (s->rtsr & (1 << 12))

        s->last_swcr += (rt - s->last_sw) / 10;

    s->last_sw = rt;
@@ -860,7 +860,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) 


static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)

{

    int64_t rt = qemu_get_clock_ms(rtc_clock);

    int64_t rt = qemu_clock_get_ms(rtc_clock);

    if (s->rtsr & (1 << 15))

        s->last_swcr += rt - s->last_pi;

    s->last_pi = rt;
@@ -986,16 +986,19 @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, 
    case PIAR:

        return s->piar;

    case RCNR:

        return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /

        return s->last_rcnr +

            ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /

            (1000 * ((s->rttr & 0xffff) + 1));

    case RDCR:

        return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /

        return s->last_rdcr +

            ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /

            (1000 * ((s->rttr & 0xffff) + 1));

    case RYCR:

        return s->last_rycr;

    case SWCR:

        if (s->rtsr & (1 << 12))

            return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10;

            return s->last_swcr +

                (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;

        else

            return s->last_swcr;

    default:
@@ -1135,14 +1138,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev) 
    s->last_swcr = (tm.tm_hour << 19) |

            (tm.tm_min << 13) | (tm.tm_sec << 7);

    s->last_rtcpicr = 0;

    s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock);



    s->rtc_hz    = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick,    s);

    s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);

    s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);

    s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);

    s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);

    s->rtc_pi    = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick,    s);

    s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);



    s->rtc_hz    = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick,    s);

    s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);

    s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);

    s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);

    s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);

    s->rtc_pi    = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick,    s);



    sysbus_init_irq(dev, &s->rtc_irq);

hw/arm/strongarm.c

+5 −5
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ static inline void strongarm_rtc_int_update(StrongARMRTCState *s) 


static void strongarm_rtc_hzupdate(StrongARMRTCState *s)

{

    int64_t rt = qemu_get_clock_ms(rtc_clock);

    int64_t rt = qemu_clock_get_ms(rtc_clock);

    s->last_rcnr += ((rt - s->last_hz) << 15) /

            (1000 * ((s->rttr & 0xffff) + 1));

    s->last_hz = rt;
@@ -322,7 +322,7 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, 
        return s->rtar;

    case RCNR:

        return s->last_rcnr +

                ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /

                ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /

                (1000 * ((s->rttr & 0xffff) + 1));

    default:

        printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
@@ -388,10 +388,10 @@ static int strongarm_rtc_init(SysBusDevice *dev) 
    qemu_get_timedate(&tm, 0);



    s->last_rcnr = (uint32_t) mktimegm(&tm);

    s->last_hz = qemu_get_clock_ms(rtc_clock);

    s->last_hz = qemu_clock_get_ms(rtc_clock);



    s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);

    s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);

    s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);

    s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);



    sysbus_init_irq(dev, &s->rtc_irq);

    sysbus_init_irq(dev, &s->rtc_hz_irq);

hw/timer/m48t59.c

+2 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static void alarm_cb (void *opaque) 
        /* Repeat once a second */

        next_time = 1;

    }

    qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +

    qemu_mod_timer(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +

                    next_time * 1000);

    qemu_set_irq(NVRAM->IRQ, 0);

}
@@ -700,7 +700,7 @@ static void m48t59_realize_common(M48t59State *s, Error **errp) 
{

    s->buffer = g_malloc0(s->size);

    if (s->model == 59) {

        s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);

        s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);

        s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);

    }

    qemu_get_timedate(&s->alarm, 0);

hw/timer/mc146818rtc.c

+15 −13
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static inline bool rtc_running(RTCState *s) 
static uint64_t get_guest_rtc_ns(RTCState *s)

{

    uint64_t guest_rtc;

    uint64_t guest_clock = qemu_get_clock_ns(rtc_clock);

    uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);



    guest_rtc = s->base_rtc * NSEC_PER_SEC

                 + guest_clock - s->last_update + s->offset;
@@ -117,7 +117,7 @@ static void rtc_coalesced_timer_update(RTCState *s) 
    } else {

        /* divide each RTC interval to 2 - 8 smaller intervals */

        int c = MIN(s->irq_coalesced, 7) + 1; 

        int64_t next_clock = qemu_get_clock_ns(rtc_clock) +

        int64_t next_clock = qemu_clock_get_ns(rtc_clock) +

            muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);

        qemu_mod_timer(s->coalesced_timer, next_clock);

    }
@@ -238,7 +238,7 @@ static void check_update_timer(RTCState *s) 


    guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;

    /* if UF is clear, reprogram to next second */

    next_update_time = qemu_get_clock_ns(rtc_clock)

    next_update_time = qemu_clock_get_ns(rtc_clock)

        + NSEC_PER_SEC - guest_nsec;



    /* Compute time of next alarm.  One second is already accounted
@@ -371,7 +371,7 @@ static void rtc_update_timer(void *opaque) 
    rtc_update_time(s);

    s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;



    if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) {

    if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {

        irqs |= REG_C_AF;

        if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {

            qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
@@ -445,7 +445,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, 
            /* UIP bit is read only */

            s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |

                (s->cmos_data[RTC_REG_A] & REG_A_UIP);

            periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));

            periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));

            check_update_timer(s);

            break;

        case RTC_REG_B:
@@ -475,7 +475,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, 
                qemu_irq_lower(s->irq);

            }

            s->cmos_data[RTC_REG_B] = data;

            periodic_timer_update(s, qemu_get_clock_ns(rtc_clock));

            periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));

            check_update_timer(s);

            break;

        case RTC_REG_C:
@@ -535,7 +535,7 @@ static void rtc_set_time(RTCState *s) 


    rtc_get_time(s, &tm);

    s->base_rtc = mktimegm(&tm);

    s->last_update = qemu_get_clock_ns(rtc_clock);

    s->last_update = qemu_clock_get_ns(rtc_clock);



    rtc_change_mon_event(&tm);

}
@@ -590,7 +590,8 @@ static int update_in_progress(RTCState *s) 
    if (timer_pending(s->update_timer)) {

        int64_t next_update_time = timer_expire_time_ns(s->update_timer);

        /* Latch UIP until the timer expires.  */

        if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) {

        if (qemu_clock_get_ns(rtc_clock) >=

            (next_update_time - UIP_HOLD_LENGTH)) {

            s->cmos_data[RTC_REG_A] |= REG_A_UIP;

            return 1;

        }
@@ -695,7 +696,7 @@ static void rtc_set_date_from_host(ISADevice *dev) 
    qemu_get_timedate(&tm, 0);



    s->base_rtc = mktimegm(&tm);

    s->last_update = qemu_get_clock_ns(rtc_clock);

    s->last_update = qemu_clock_get_ns(rtc_clock);

    s->offset = 0;



    /* set the CMOS date */
@@ -843,7 +844,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) 
    switch (s->lost_tick_policy) {

    case LOST_TICK_SLEW:

        s->coalesced_timer =

            qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);

            timer_new_ns(rtc_clock, rtc_coalesced_timer, s);

        break;

    case LOST_TICK_DISCARD:

        break;
@@ -853,12 +854,13 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) 
    }

#endif



    s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);

    s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s);

    s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);

    s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);

    check_update_timer(s);



    s->clock_reset_notifier.notify = rtc_notify_clock_reset;

    qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);

    qemu_clock_register_reset_notifier(QEMU_CLOCK_REALTIME,

                                       &s->clock_reset_notifier);



    s->suspend_notifier.notify = rtc_notify_suspend;

    qemu_register_suspend_notifier(&s->suspend_notifier);