Commit 87562e4f authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Enable the AArch32 ATS12NSO ops 



Apply the correct conditions in the ats_access() function for
the ATS12NSO* address translation operations:
 * succeed at EL2 or EL3
 * normal UNDEF trap from NS EL1
 * trap to EL3 from S EL1 (only possible if EL3 is AArch64)

(This change means they're now available in our EL3-supporting
CPUs when they would previously always UNDEF.)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
parent e7615726

target-arm/helper.c

+11 −5
Original line number Diff line number Diff line
@@ -1719,13 +1719,18 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) 
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)

{

    if (ri->opc2 & 4) {

        /* Other states are only available with TrustZone; in

         * a non-TZ implementation these registers don't exist

         * at all, which is an Uncategorized trap. This underdecoding

         * is safe because the reginfo is NO_RAW.

        /* The ATS12NSO* operations must trap to EL3 if executed in

         * Secure EL1 (which can only happen if EL3 is AArch64).

         * They are simply UNDEF if executed from NS EL1.

         * They function normally from EL2 or EL3.

         */

        if (arm_current_el(env) == 1) {

            if (arm_is_secure_below_el3(env)) {

                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;

            }

            return CP_ACCESS_TRAP_UNCATEGORIZED;

        }

    }

    return CP_ACCESS_OK;

}
@@ -1899,6 +1904,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { 
                             offsetoflow32(CPUARMState, cp15.par_ns) },

      .writefn = par_write },

#ifndef CONFIG_USER_ONLY

    /* This underdecoding is safe because the reginfo is NO_RAW. */

    { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,

      .access = PL1_W, .accessfn = ats_access,

      .writefn = ats_write, .type = ARM_CP_NO_RAW },