Commit 86cbc418 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT 



Implement the 2-reg-misc CNT, NOT and RBIT instructions.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
parent 94b6c911

target-arm/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -320,6 +320,7 @@ DEF_HELPER_1(neon_cls_s8, i32, i32) 
DEF_HELPER_1(neon_cls_s16, i32, i32)

DEF_HELPER_1(neon_cls_s32, i32, i32)

DEF_HELPER_1(neon_cnt_u8, i32, i32)

DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)



DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)

DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)

target-arm/neon_helper.c

+12 −0
Original line number Diff line number Diff line
@@ -1133,6 +1133,18 @@ uint32_t HELPER(neon_cnt_u8)(uint32_t x) 
    return x;

}



/* Reverse bits in each 8 bit word */

uint32_t HELPER(neon_rbit_u8)(uint32_t x)

{

    x =  ((x & 0xf0f0f0f0) >> 4)

       | ((x & 0x0f0f0f0f) << 4);

    x =  ((x & 0x88888888) >> 3)

       | ((x & 0x44444444) >> 1)

       | ((x & 0x22222222) << 1)

       | ((x & 0x11111111) << 3);

    return x;

}



#define NEON_QDMULH16(dest, src1, src2, round) do { \

    uint32_t tmp = (int32_t)(int16_t) src1 * (int16_t) src2; \

    if ((tmp ^ (tmp << 1)) & SIGNBIT) { \

target-arm/translate-a64.c

+28 −6
Original line number Diff line number Diff line
@@ -6222,6 +6222,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, 
    TCGCond cond;



    switch (opcode) {

    case 0x5: /* NOT */

        /* This opcode is shared with CNT and RBIT but we have earlier

         * enforced that size == 3 if and only if this is the NOT insn.

         */

        tcg_gen_not_i64(tcg_rd, tcg_rn);

        break;

    case 0xa: /* CMLT */

        /* 64 bit integer comparison against zero, result is

         * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
@@ -7386,12 +7392,18 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) 
        unsupported_encoding(s, insn);

        return;

    case 0x5: /* CNT, NOT, RBIT */

        if ((u == 0 && size > 0) ||

            (u == 1 && size > 1)) {

            unallocated_encoding(s);

            return;

        if (u && size == 0) {

            /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */

            size = 3;

            break;

        } else if (u && size == 1) {

            /* RBIT */

            break;

        } else if (!u && size == 0) {

            /* CNT */

            break;

        }

        unsupported_encoding(s, insn);

        unallocated_encoding(s);

        return;

    case 0x2: /* SADDLP, UADDLP */

    case 0x4: /* CLS, CLZ */
@@ -7553,6 +7565,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) 
            } else {

                /* Use helpers for 8 and 16 bit elements */

                switch (opcode) {

                case 0x5: /* CNT, RBIT */

                    /* For these two insns size is part of the opcode specifier

                     * (handled earlier); they always operate on byte elements.

                     */

                    if (u) {

                        gen_helper_neon_rbit_u8(tcg_res, tcg_op);

                    } else {

                        gen_helper_neon_cnt_u8(tcg_res, tcg_op);

                    }

                    break;

                case 0x8: /* CMGT, CMGE */

                case 0x9: /* CMEQ, CMLE */

                case 0xa: /* CMLT */