Commit 866ad5f5 authored by BALATON Zoltan's avatar BALATON Zoltan Committed by Gerd Hoffmann
Browse files

ati-vga: Fixes to offset and pitch registers 



Fix bit masks of registers for offset and pitch and also handle
default values for both R128P and RV100. This improves picture a bit
but does not resolve all problems yet so there might be some more bugs
somewhere.

Signed-off-by: default avatarBALATON Zoltan <balaton@eik.bme.hu>
Message-id: 20190624100005.7A1CA746395@zero.eik.bme.hu
Signed-off-by: default avatarGerd Hoffmann <kraxel@redhat.com>
parent c82c7336

hw/display/ati.c

+22 −10
Original line number Diff line number Diff line
@@ -419,9 +419,15 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 
        break;

    case DEFAULT_OFFSET:

        val = s->regs.default_offset;

        if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {

            val >>= 10;

            val |= s->regs.default_pitch << 16;

            val |= s->regs.default_tile << 30;

        }

        break;

    case DEFAULT_PITCH:

        val = s->regs.default_pitch;

        val |= s->regs.default_tile << 16;

        break;

    case DEFAULT_SC_BOTTOM_RIGHT:

        val = s->regs.default_sc_bottom_right;
@@ -682,22 +688,22 @@ static void ati_mm_write(void *opaque, hwaddr addr, 
        break;

    case SRC_PITCH_OFFSET:

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.src_offset = (data & 0x1fffff) << 5;

            s->regs.src_pitch = (data >> 21) & 0x3ff;

            s->regs.src_offset = (data & 0x1fffff) << 4;

            s->regs.src_pitch = (data & 0x7fe00000) >> 21;

            s->regs.src_tile = data >> 31;

        } else {

            s->regs.src_offset = (data & 0x3fffff) << 11;

            s->regs.src_offset = (data & 0x3fffff) << 10;

            s->regs.src_pitch = (data & 0x3fc00000) >> 16;

            s->regs.src_tile = (data >> 30) & 1;

        }

        break;

    case DST_PITCH_OFFSET:

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.dst_offset = (data & 0x1fffff) << 5;

            s->regs.dst_pitch = (data >> 21) & 0x3ff;

            s->regs.dst_offset = (data & 0x1fffff) << 4;

            s->regs.dst_pitch = (data & 0x7fe00000) >> 21;

            s->regs.dst_tile = data >> 31;

        } else {

            s->regs.dst_offset = (data & 0x3fffff) << 11;

            s->regs.dst_offset = (data & 0x3fffff) << 10;

            s->regs.dst_pitch = (data & 0x3fc00000) >> 16;

            s->regs.dst_tile = data >> 30;

        }
@@ -777,13 +783,19 @@ static void ati_mm_write(void *opaque, hwaddr addr, 
        s->regs.dp_write_mask = data;

        break;

    case DEFAULT_OFFSET:

        data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?

                 0x03fffc00 : 0xfffffc00);

        s->regs.default_offset = data;

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.default_offset = data & 0xfffffff0;

        } else {

            /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */

            s->regs.default_offset = (data & 0x3fffff) << 10;

            s->regs.default_pitch = (data & 0x3fc00000) >> 16;

            s->regs.default_tile = data >> 30;

        }

        break;

    case DEFAULT_PITCH:

        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            s->regs.default_pitch = data & 0x103ff;

            s->regs.default_pitch = data & 0x3fff;

            s->regs.default_tile = (data >> 16) & 1;

        }

        break;

    case DEFAULT_SC_BOTTOM_RIGHT:

hw/display/ati_2d.c

+18 −8
Original line number Diff line number Diff line
@@ -51,8 +51,9 @@ void ati_2d_blt(ATIVGAState *s) 
            s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),

            surface_bits_per_pixel(ds),

            (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);

    DPRINTF("%d %d, %d %d, (%d,%d) -> (%d,%d) %dx%d\n", s->regs.src_offset,

            s->regs.dst_offset, s->regs.src_pitch, s->regs.dst_pitch,

    DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n",

            s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,

            s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,

            s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,

            s->regs.dst_width, s->regs.dst_height);

    switch (s->regs.dp_mix & GMC_ROP3_MASK) {
@@ -60,10 +61,16 @@ void ati_2d_blt(ATIVGAState *s) 
    {

        uint8_t *src_bits, *dst_bits, *end;

        int src_stride, dst_stride, bpp = ati_bpp_from_datatype(s);

        src_bits = s->vga.vram_ptr + s->regs.src_offset;

        dst_bits = s->vga.vram_ptr + s->regs.dst_offset;

        src_stride = s->regs.src_pitch;

        dst_stride = s->regs.dst_pitch;

        src_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ?

                    s->regs.src_offset : s->regs.default_offset);

        dst_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                    s->regs.dst_offset : s->regs.default_offset);

        src_stride = (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ?

                      s->regs.src_pitch : s->regs.default_pitch);

        dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                      s->regs.dst_pitch : s->regs.default_pitch);



        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            src_bits += s->regs.crtc_offset & 0x07ffffff;
@@ -111,8 +118,11 @@ void ati_2d_blt(ATIVGAState *s) 
        uint8_t *dst_bits, *end;

        int dst_stride, bpp = ati_bpp_from_datatype(s);

        uint32_t filler = 0;

        dst_bits = s->vga.vram_ptr + s->regs.dst_offset;

        dst_stride = s->regs.dst_pitch;

        dst_bits = s->vga.vram_ptr +

                   (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                    s->regs.dst_offset : s->regs.default_offset);

        dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ?

                      s->regs.dst_pitch : s->regs.default_pitch);



        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {

            dst_bits += s->regs.crtc_offset & 0x07ffffff;

hw/display/ati_int.h

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ typedef struct ATIVGARegs { 
    uint32_t dp_write_mask;

    uint32_t default_offset;

    uint32_t default_pitch;

    uint32_t default_tile;

    uint32_t default_sc_bottom_right;

} ATIVGARegs;

hw/display/ati_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -370,8 +370,8 @@ 
#define BRUSH_SOLIDCOLOR                        0x00000d00



/* DP_GUI_MASTER_CNTL bit constants */

#define GMC_SRC_PITCH_OFFSET_DEFAULT            0x00000000

#define GMC_DST_PITCH_OFFSET_DEFAULT            0x00000000

#define GMC_SRC_PITCH_OFFSET_CNTL               0x00000001

#define GMC_DST_PITCH_OFFSET_CNTL               0x00000002

#define GMC_SRC_CLIP_DEFAULT                    0x00000000

#define GMC_DST_CLIP_DEFAULT                    0x00000000

#define GMC_BRUSH_SOLIDCOLOR                    0x000000d0