Commit 84108e12 authored by Blue Swirl's avatar Blue Swirl
Browse files

Compile isa_mmio only once 



Push TARGET_WORDS_BIGENDIAN dependency to board level.

Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
parent 7161e571

Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ hw-obj-y += loader.o 
hw-obj-y += virtio.o virtio-console.o

hw-obj-y += fw_cfg.o

hw-obj-y += watchdog.o

hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o

hw-obj-$(CONFIG_ECC) += ecc.o

hw-obj-$(CONFIG_NAND) += nand.o

Makefile.target

+0 −1
Original line number Diff line number Diff line
@@ -168,7 +168,6 @@ obj-y += qemu-timer.o 
obj-y += virtio-blk.o virtio-balloon.o virtio-net.o virtio-pci.o virtio-serial-bus.o

obj-y += rwhandler.o

obj-$(CONFIG_KVM) += kvm.o kvm-all.o

obj-$(CONFIG_ISA_MMIO) += isa_mmio.o

LIBS+=-lz



sound-obj-y =

hw/gt64xxx.c

+5 −1
Original line number Diff line number Diff line
@@ -297,7 +297,11 @@ static void gt64120_pci_mapping(GT64120State *s) 
      s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;

      s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;

      isa_mem_base = s->PCI0IO_start;

      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);

#ifdef TARGET_WORDS_BIGENDIAN

      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 1);

#else

      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 0);

#endif

    }

}

hw/isa.h

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ ISADevice *isa_create_simple(const char *name); 


extern target_phys_addr_t isa_mem_base;



void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);

void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);



/* dma.c */

int DMA_get_channel_mode (int nchan);

hw/isa_mmio.c

+62 −23
Original line number Diff line number Diff line
@@ -31,21 +31,29 @@ static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, 
    cpu_outb(addr & IOPORTS_MASK, val);

}



static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,

static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,

                               uint32_t val)

{

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    cpu_outw(addr & IOPORTS_MASK, val);

}



static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,

static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,

                               uint32_t val)

{

    cpu_outw(addr & IOPORTS_MASK, val);

}



static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,

                               uint32_t val)

{

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    cpu_outl(addr & IOPORTS_MASK, val);

}



static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,

                               uint32_t val)

{

    cpu_outl(addr & IOPORTS_MASK, val);

}
@@ -57,47 +65,78 @@ static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) 
    return val;

}



static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)

static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)

{

    uint32_t val;



    val = cpu_inw(addr & IOPORTS_MASK);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap16(val);

#endif

    return val;

}



static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)

static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)

{

    uint32_t val;



    val = cpu_inw(addr & IOPORTS_MASK);

    return val;

}



static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)

{

    uint32_t val;



    val = cpu_inl(addr & IOPORTS_MASK);

#ifdef TARGET_WORDS_BIGENDIAN

    val = bswap32(val);

#endif

    return val;

}



static CPUWriteMemoryFunc * const isa_mmio_write[] = {

static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)

{

    uint32_t val;



    val = cpu_inl(addr & IOPORTS_MASK);

    return val;

}



static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {

    &isa_mmio_writeb,

    &isa_mmio_writew,

    &isa_mmio_writel,

    &isa_mmio_writew_be,

    &isa_mmio_writel_be,

};



static CPUReadMemoryFunc * const isa_mmio_read[] = {

static CPUReadMemoryFunc * const isa_mmio_read_be[] = {

    &isa_mmio_readb,

    &isa_mmio_readw,

    &isa_mmio_readl,

    &isa_mmio_readw_be,

    &isa_mmio_readl_be,

};



static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {

    &isa_mmio_writeb,

    &isa_mmio_writew_le,

    &isa_mmio_writel_le,

};



static CPUReadMemoryFunc * const isa_mmio_read_le[] = {

    &isa_mmio_readb,

    &isa_mmio_readw_le,

    &isa_mmio_readl_le,

};



static int isa_mmio_iomemtype = 0;



void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)

void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)

{

    if (!isa_mmio_iomemtype) {

        isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,

                                                    isa_mmio_write, NULL);

        if (be) {

            isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,

                                                        isa_mmio_write_be,

                                                        NULL);

        } else {

            isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,

                                                        isa_mmio_write_le,

                                                        NULL);

        }

    }

    cpu_register_physical_memory(base, size, isa_mmio_iomemtype);

}