Commit 8351ef7a authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-26-2019' into staging 



MIPS queue for June 2016th, 2019

# gpg: Signature made Wed 26 Jun 2019 12:38:58 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-26-2019:
  target/mips: Fix big endian host behavior for interleave MSA instructions
  tests/tcg: target/mips: Fix some test cases for pack MSA instructions
  tests/tcg: target/mips: Add support for MSA MIPS32R6 testings
  tests/tcg: target/mips: Add support for MSA big-endian target testings
  tests/tcg: target/mips: Amend tests for MSA int multiply instructions
  tests/tcg: target/mips: Amend tests for MSA int dot product instructions
  tests/tcg: target/mips: Add tests for MSA move instructions
  tests/tcg: target/mips: Add tests for MSA bit move instructions
  dma/rc4030: Minor code style cleanup
  dma/rc4030: Fix off-by-one error in specified memory region size
  hw/mips/gt64xxx_pci: Align the pci0-mem size
  hw/mips/gt64xxx_pci: Convert debug printf()s to trace events
  hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()
  hw/mips/gt64xxx_pci: Fix 'spaces' coding style issues
  hw/mips/gt64xxx_pci: Fix 'braces' coding style issues
  hw/mips/gt64xxx_pci: Fix 'tabs' coding style issues
  hw/mips/gt64xxx_pci: Fix multiline comment syntax

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 39d1b92b 5a6a1fab

Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ trace-events-subdirs += hw/input 
trace-events-subdirs += hw/intc

trace-events-subdirs += hw/isa

trace-events-subdirs += hw/mem

trace-events-subdirs += hw/mips

trace-events-subdirs += hw/misc

trace-events-subdirs += hw/misc/macio

trace-events-subdirs += hw/net

hw/dma/rc4030.c

+13 −8
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/units.h"

#include "hw/hw.h"

#include "hw/mips/mips.h"

#include "hw/sysbus.h"
@@ -57,8 +58,8 @@ typedef struct dma_pagetable_entry { 


#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"



typedef struct rc4030State

{

typedef struct rc4030State {



    SysBusDevice parent;



    uint32_t config; /* 0x0000: RC4030 config register */
@@ -151,8 +152,9 @@ static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) 
    case 0x0058:

        val = s->cache_bmask;

        /* HACK */

        if (s->cache_bmask == (uint32_t)-1)

        if (s->cache_bmask == (uint32_t)-1) {

            s->cache_bmask = 0;

        }

        break;

    /* Remote Speed Registers */

    case 0x0070:
@@ -537,8 +539,9 @@ static void rc4030_reset(DeviceState *dev) 


    s->memory_refresh_rate = 0x18186;

    s->nvram_protect = 7;

    for (i = 0; i < 15; i++)

    for (i = 0; i < 15; i++) {

        s->rem_speed[i] = 7;

    }

    s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */

    s->isr_jazz = 0;
@@ -590,7 +593,8 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri 
    hwaddr dma_addr;

    int dev_to_mem;



    s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);

    s->dma_regs[n][DMA_REG_ENABLE] &=

           ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);



    /* Check DMA channel consistency */

    dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
@@ -602,8 +606,9 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri 
    }



    /* Get start address and len */

    if (len > s->dma_regs[n][DMA_REG_COUNT])

    if (len > s->dma_regs[n][DMA_REG_COUNT]) {

        len = s->dma_regs[n][DMA_REG_COUNT];

    }

    dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];



    /* Read/write data at right place */
@@ -678,7 +683,7 @@ static void rc4030_realize(DeviceState *dev, Error **errp) 


    memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),

                             TYPE_RC4030_IOMMU_MEMORY_REGION,

                             o, "rc4030.dma", UINT32_MAX);

                             o, "rc4030.dma", 4 * GiB);

    address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");

}

hw/mips/gt64xxx_pci.c

+264 −230
Original line number Diff line number Diff line
@@ -23,20 +23,15 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/units.h"

#include "qemu/log.h"

#include "hw/hw.h"

#include "hw/mips/mips.h"

#include "hw/pci/pci.h"

#include "hw/pci/pci_host.h"

#include "hw/i386/pc.h"

#include "exec/address-spaces.h"



//#define DEBUG



#ifdef DEBUG

#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)

#else

#define DPRINTF(fmt, ...)

#endif

#include "trace.h"



#define GT_REGS                 (0x1000 >> 2)
@@ -248,27 +243,34 @@ typedef struct GT64120State { 
} GT64120State;



/* Adjust range to avoid touching space which isn't mappable via PCI */

/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000

                                    0x1fc00000 - 0x1fd00000  */

static void check_reserved_space (hwaddr *start,

                                  hwaddr *length)

/*

 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000

 *                                  0x1fc00000 - 0x1fd00000

 */

static void check_reserved_space(hwaddr *start, hwaddr *length)

{

    hwaddr begin = *start;

    hwaddr end = *start + *length;



    if (end >= 0x1e000000LL && end < 0x1f100000LL)

    if (end >= 0x1e000000LL && end < 0x1f100000LL) {

        end = 0x1e000000LL;

    if (begin >= 0x1e000000LL && begin < 0x1f100000LL)

    }

    if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {

        begin = 0x1f100000LL;

    if (end >= 0x1fc00000LL && end < 0x1fd00000LL)

    }

    if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {

        end = 0x1fc00000LL;

    if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)

    }

    if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {

        begin = 0x1fd00000LL;

    }

    /* XXX: This is broken when a reserved range splits the requested range */

    if (end >= 0x1f100000LL && begin < 0x1e000000LL)

    if (end >= 0x1f100000LL && begin < 0x1e000000LL) {

        end = 0x1e000000LL;

    if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)

    }

    if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {

        end = 0x1fc00000LL;

    }



    *start = begin;

    *length = end - begin;
@@ -286,9 +288,7 @@ static void gt64120_isd_mapping(GT64120State *s) 
    check_reserved_space(&start, &length);

    length = 0x1000;

    /* Map new address */

    DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx

        " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",

        s->ISD_length, s->ISD_start, length, start);

    trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);

    s->ISD_start = start;

    s->ISD_length = length;

    memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
@@ -384,8 +384,9 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    PCIHostState *phb = PCI_HOST_BRIDGE(s);

    uint32_t saddr;



    if (!(s->regs[GT_CPU] & 0x00001000))

    if (!(s->regs[GT_CPU] & 0x00001000)) {

        val = bswap32(val);

    }



    saddr = (addr & 0xfff) >> 2;

    switch (saddr) {
@@ -458,12 +459,20 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_CPUERR_DATAHI:

    case GT_CPUERR_PARITY:

        /* Read-only registers, do nothing */

        qemu_log_mask(LOG_GUEST_ERROR,

                      "gt64120: Read-only register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* CPU Sync Barrier */

    case GT_PCI0SYNC:

    case GT_PCI1SYNC:

        /* Read-only registers, do nothing */

        qemu_log_mask(LOG_GUEST_ERROR,

                      "gt64120: Read-only register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* SDRAM and Device Address Decode */
@@ -502,7 +511,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_DEV_B3:

    case GT_DEV_BOOT:

        /* Not implemented */

        DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);

        qemu_log_mask(LOG_UNIMP,

                      "gt64120: Unimplemented device register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* ECC */
@@ -512,6 +524,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_ECC_CALC:

    case GT_ECC_ERRADDR:

        /* Read-only registers, do nothing */

        qemu_log_mask(LOG_GUEST_ERROR,

                      "gt64120: Read-only register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* DMA Record */
@@ -535,23 +551,20 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_DMA1_CUR:

    case GT_DMA2_CUR:

    case GT_DMA3_CUR:

        /* Not implemented */

        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);

        break;



    /* DMA Channel Control */

    case GT_DMA0_CTRL:

    case GT_DMA1_CTRL:

    case GT_DMA2_CTRL:

    case GT_DMA3_CTRL:

        /* Not implemented */

        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);

        break;



    /* DMA Arbiter */

    case GT_DMA_ARB:

        /* Not implemented */

        DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);

        qemu_log_mask(LOG_UNIMP,

                      "gt64120: Unimplemented DMA register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* Timer/Counter */
@@ -561,7 +574,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_TC3:

    case GT_TC_CONTROL:

        /* Not implemented */

        DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);

        qemu_log_mask(LOG_UNIMP,

                      "gt64120: Unimplemented timer register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;



    /* PCI Internal */
@@ -602,6 +618,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_PCI1_CFGADDR:

    case GT_PCI1_CFGDATA:

        /* not implemented */

        qemu_log_mask(LOG_UNIMP,

                      "gt64120: Unimplemented timer register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;

    case GT_PCI0_CFGADDR:

        phb->config_reg = val & 0x80fffffc;
@@ -620,19 +640,19 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
        /* not really implemented */

        s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));

        s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);

        DPRINTF("INTRCAUSE %" PRIx64 "\n", val);

        trace_gt64120_write("INTRCAUSE", size << 1, val);

        break;

    case GT_INTRMASK:

        s->regs[saddr] = val & 0x3c3ffffe;

        DPRINTF("INTRMASK %" PRIx64 "\n", val);

        trace_gt64120_write("INTRMASK", size << 1, val);

        break;

    case GT_PCI0_ICMASK:

        s->regs[saddr] = val & 0x03fffffe;

        DPRINTF("ICMASK %" PRIx64 "\n", val);

        trace_gt64120_write("ICMASK", size << 1, val);

        break;

    case GT_PCI0_SERR0MASK:

        s->regs[saddr] = val & 0x0000003f;

        DPRINTF("SERR0MASK %" PRIx64 "\n", val);

        trace_gt64120_write("SERR0MASK", size << 1, val);

        break;



    /* Reserved when only PCI_0 is configured. */
@@ -650,13 +670,18 @@ static void gt64120_writel (void *opaque, hwaddr addr, 
    case GT_SDRAM_B1:

    case GT_SDRAM_B2:

    case GT_SDRAM_B3:

        /* We don't simulate electrical parameters of the SDRAM.

           Accept, but ignore the values. */

        /*

         * We don't simulate electrical parameters of the SDRAM.

         * Accept, but ignore the values.

         */

        s->regs[saddr] = val;

        break;



    default:

        DPRINTF ("Bad register offset 0x%x\n", (int)addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "gt64120: Illegal register write "

                      "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",

                      saddr << 2, size, size << 1, val);

        break;

    }

}
@@ -674,8 +699,10 @@ static uint64_t gt64120_readl (void *opaque, 


    /* CPU Configuration */

    case GT_MULTI:

        /* Only one GT64xxx is present on the CPU bus, return

           the initial value */

        /*

         * Only one GT64xxx is present on the CPU bus, return

         * the initial value.

         */

        val = s->regs[saddr];

        break;
@@ -685,17 +712,18 @@ static uint64_t gt64120_readl (void *opaque, 
    case GT_CPUERR_DATALO:

    case GT_CPUERR_DATAHI:

    case GT_CPUERR_PARITY:

        /* Emulated memory has no error, always return the initial

           values */

        /* Emulated memory has no error, always return the initial values. */

        val = s->regs[saddr];

        break;



    /* CPU Sync Barrier */

    case GT_PCI0SYNC:

    case GT_PCI1SYNC:

        /* Reading those register should empty all FIFO on the PCI

           bus, which are not emulated. The return value should be

           a random value that should be ignored. */

        /*

         * Reading those register should empty all FIFO on the PCI

         * bus, which are not emulated. The return value should be

         * a random value that should be ignored.

         */

        val = 0xc000ffee;

        break;
@@ -705,8 +733,7 @@ static uint64_t gt64120_readl (void *opaque, 
    case GT_ECC_MEM:

    case GT_ECC_CALC:

    case GT_ECC_ERRADDR:

        /* Emulated memory has no error, always return the initial

           values */

        /* Emulated memory has no error, always return the initial values. */

        val = s->regs[saddr];

        break;
@@ -785,8 +812,10 @@ static uint64_t gt64120_readl (void *opaque, 
    case GT_SDRAM_B1:

    case GT_SDRAM_B2:

    case GT_SDRAM_B3:

        /* We don't simulate electrical parameters of the SDRAM.

           Just return the last written value. */

        /*

         * We don't simulate electrical parameters of the SDRAM.

         * Just return the last written value.

         */

        val = s->regs[saddr];

        break;
@@ -899,19 +928,19 @@ static uint64_t gt64120_readl (void *opaque, 
    /* Interrupts */

    case GT_INTRCAUSE:

        val = s->regs[saddr];

        DPRINTF("INTRCAUSE %x\n", val);

        trace_gt64120_read("INTRCAUSE", size << 1, val);

        break;

    case GT_INTRMASK:

        val = s->regs[saddr];

        DPRINTF("INTRMASK %x\n", val);

        trace_gt64120_read("INTRMASK", size << 1, val);

        break;

    case GT_PCI0_ICMASK:

        val = s->regs[saddr];

        DPRINTF("ICMASK %x\n", val);

        trace_gt64120_read("ICMASK", size << 1, val);

        break;

    case GT_PCI0_SERR0MASK:

        val = s->regs[saddr];

        DPRINTF("SERR0MASK %x\n", val);

        trace_gt64120_read("SERR0MASK", size << 1, val);

        break;



    /* Reserved when only PCI_0 is configured. */
@@ -926,12 +955,16 @@ static uint64_t gt64120_readl (void *opaque, 


    default:

        val = s->regs[saddr];

        DPRINTF ("Bad register offset 0x%x\n", (int)addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "gt64120: Illegal register read "

                      "reg:0x03%x size:%u value:0x%0*x\n",

                      saddr << 2, size, size << 1, val);

        break;

    }



    if (!(s->regs[GT_CPU] & 0x00001000))

    if (!(s->regs[GT_CPU] & 0x00001000)) {

        val = bswap32(val);

    }



    return val;

}
@@ -980,13 +1013,13 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) 
    /* XXX: optimize */

    pic_irq = piix4_dev->config[0x60 + irq_num];

    if (pic_irq < 16) {

        /* The pic level is the logical OR of all the PCI irqs mapped

           to it */

        /* The pic level is the logical OR of all the PCI irqs mapped to it. */

        pic_level = 0;

        for (i = 0; i < 4; i++) {

            if (pic_irq == piix4_dev->config[0x60 + i])

            if (pic_irq == piix4_dev->config[0x60 + i]) {

                pic_level |= pci_irq_levels[i];

            }

        }

        qemu_set_irq(pic[pic_irq], pic_level);

    }

}
@@ -1169,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic) 
    dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);

    d = GT64120_PCI_HOST_BRIDGE(dev);

    phb = PCI_HOST_BRIDGE(dev);

    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);

    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);

    address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");

    phb->bus = pci_register_root_bus(dev, "pci",

                                     gt64120_pci_set_irq, gt64120_pci_map_irq,
@@ -1178,7 +1211,8 @@ PCIBus *gt64120_register(qemu_irq *pic) 
                                     get_system_io(),

                                     PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);

    qdev_init_nofail(dev);

    memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);

    memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,

                          "isd-mem", 0x1000);



    pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");

    return phb->bus;

hw/mips/trace-events

0 → 100644
+4 −0
Original line number Diff line number Diff line 
# gt64xxx.c

gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64

gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64

gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64

target/mips/msa_helper.c

+12 −12
Original line number Diff line number Diff line
@@ -1737,7 +1737,7 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->b[8]  = pws->b[9];

        pwd->b[9]  = pwt->b[9];

        pwd->b[10] = pws->b[11];
@@ -1774,7 +1774,7 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->h[4] = pws->h[5];

        pwd->h[5] = pwt->h[5];

        pwd->h[6] = pws->h[7];
@@ -1795,7 +1795,7 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->w[2] = pws->w[3];

        pwd->w[3] = pwt->w[3];

        pwd->w[0] = pws->w[1];
@@ -1825,7 +1825,7 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->b[7]  = pwt->b[6];

        pwd->b[6]  = pws->b[6];

        pwd->b[5]  = pwt->b[4];
@@ -1862,7 +1862,7 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->h[3] = pwt->h[2];

        pwd->h[2] = pws->h[2];

        pwd->h[1] = pwt->h[0];
@@ -1883,7 +1883,7 @@ void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->w[1] = pwt->w[0];

        pwd->w[0] = pws->w[0];

        pwd->w[3] = pwt->w[2];
@@ -1913,7 +1913,7 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->b[7]  = pwt->b[15];

        pwd->b[6]  = pws->b[15];

        pwd->b[5]  = pwt->b[14];
@@ -1950,7 +1950,7 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->h[3] = pwt->h[7];

        pwd->h[2] = pws->h[7];

        pwd->h[1] = pwt->h[6];
@@ -1971,7 +1971,7 @@ void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->w[1] = pwt->w[3];

        pwd->w[0] = pws->w[3];

        pwd->w[3] = pwt->w[2];
@@ -2001,7 +2001,7 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 


    switch (df) {

    case DF_BYTE:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->b[8]  = pws->b[0];

        pwd->b[9]  = pwt->b[0];

        pwd->b[10] = pws->b[1];
@@ -2038,7 +2038,7 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_HALF:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->h[4] = pws->h[0];

        pwd->h[5] = pwt->h[0];

        pwd->h[6] = pws->h[1];
@@ -2059,7 +2059,7 @@ void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, 
#endif

        break;

    case DF_WORD:

#if defined(TARGET_WORDS_BIGENDIAN)

#if defined(HOST_WORDS_BIGENDIAN)

        pwd->w[2] = pws->w[0];

        pwd->w[3] = pwt->w[0];

        pwd->w[0] = pws->w[1];