Commit 821be9db authored by Knut Omang's avatar Knut Omang Committed by Michael S. Tsirkin
Browse files

pcie: Rename the pcie_cap_ari_* functions to pcie_cap_arifwd_* 



Rename helper functions to make a clearer distinction between
the PCIe capability/control register feature ARI forwarding and a
device that supports the ARI feature via an ARI extended PCIe capability.

Signed-off-by: default avatarKnut Omang <knut.omang@oracle.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent ec70b46b

hw/pci-bridge/ioh3420.c

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ static int ioh3420_initfn(PCIDevice *d) 
    if (rc < 0) {

        goto err_msi;

    }



    pcie_cap_deverr_init(d);

    pcie_cap_slot_init(d, s->slot);

    pcie_chassis_create(s->chassis);

hw/pci-bridge/xio3130_downstream.c

+2 −2
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static void xio3130_downstream_reset(DeviceState *qdev) 


    pcie_cap_deverr_reset(d);

    pcie_cap_slot_reset(d);

    pcie_cap_ari_reset(d);

    pcie_cap_arifwd_reset(d);

    pci_bridge_reset(qdev);

}
@@ -91,7 +91,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) 
    if (rc < 0) {

        goto err_pcie_cap;

    }

    pcie_cap_ari_init(d);

    pcie_cap_arifwd_init(d);

    rc = pcie_aer_init(d, XIO3130_AER_OFFSET);

    if (rc < 0) {

        goto err;

hw/pci/pcie.c

+6 −5
Original line number Diff line number Diff line
@@ -497,9 +497,10 @@ void pcie_cap_flr_write_config(PCIDevice *dev, 
    }

}



/* Alternative Routing-ID Interpretation (ARI) */

/* ari forwarding support for down stream port */

void pcie_cap_ari_init(PCIDevice *dev)

/* Alternative Routing-ID Interpretation (ARI)

 * forwarding support for root and downstream ports 

 */

void pcie_cap_arifwd_init(PCIDevice *dev)

{

    uint32_t pos = dev->exp.exp_cap;

    pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
@@ -508,13 +509,13 @@ void pcie_cap_ari_init(PCIDevice *dev) 
                               PCI_EXP_DEVCTL2_ARI);

}



void pcie_cap_ari_reset(PCIDevice *dev)

void pcie_cap_arifwd_reset(PCIDevice *dev)

{

    uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;

    pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);

}



bool pcie_cap_is_ari_enabled(const PCIDevice *dev)

bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)

{

    if (!pci_is_express(dev)) {

        return false;

include/hw/pci/pcie.h

+4 −3
Original line number Diff line number Diff line
@@ -103,9 +103,10 @@ void pcie_cap_flr_init(PCIDevice *dev); 
void pcie_cap_flr_write_config(PCIDevice *dev,

                           uint32_t addr, uint32_t val, int len);



void pcie_cap_ari_init(PCIDevice *dev);

void pcie_cap_ari_reset(PCIDevice *dev);

bool pcie_cap_is_ari_enabled(const PCIDevice *dev);

/* ARI forwarding capability and control */

void pcie_cap_arifwd_init(PCIDevice *dev);

void pcie_cap_arifwd_reset(PCIDevice *dev);

bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev);



/* PCI express extended capability helper functions */

uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);