Commit 81f68110 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert VFP two-register transfer insns to decodetree 



Convert the VFP two-register transfer instructions to decodetree
(in the v8 Arm ARM these are the "Advanced SIMD and floating-point
64-bit move" encoding group).

Again, we expand out the sequences involving gen_vfp_msr() and
gen_msr_vfp().

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent a9ab5001

target/arm/translate-vfp.inc.c

+70 −0
Original line number Diff line number Diff line
@@ -783,3 +783,73 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) 


    return true;

}



static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)

{

    TCGv_i32 tmp;



    /*

     * VMOV between two general-purpose registers and two single precision

     * floating point registers

     */

    if (!vfp_access_check(s)) {

        return true;

    }



    if (a->op) {

        /* fpreg to gpreg */

        tmp = tcg_temp_new_i32();

        neon_load_reg32(tmp, a->vm);

        store_reg(s, a->rt, tmp);

        tmp = tcg_temp_new_i32();

        neon_load_reg32(tmp, a->vm + 1);

        store_reg(s, a->rt2, tmp);

    } else {

        /* gpreg to fpreg */

        tmp = load_reg(s, a->rt);

        neon_store_reg32(tmp, a->vm);

        tmp = load_reg(s, a->rt2);

        neon_store_reg32(tmp, a->vm + 1);

    }



    return true;

}



static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a)

{

    TCGv_i32 tmp;



    /*

     * VMOV between two general-purpose registers and one double precision

     * floating point register

     */



    /* UNDEF accesses to D16-D31 if they don't exist */

    if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {

        return false;

    }



    if (!vfp_access_check(s)) {

        return true;

    }



    if (a->op) {

        /* fpreg to gpreg */

        tmp = tcg_temp_new_i32();

        neon_load_reg32(tmp, a->vm * 2);

        store_reg(s, a->rt, tmp);

        tmp = tcg_temp_new_i32();

        neon_load_reg32(tmp, a->vm * 2 + 1);

        store_reg(s, a->rt2, tmp);

    } else {

        /* gpreg to fpreg */

        tmp = load_reg(s, a->rt);

        neon_store_reg32(tmp, a->vm * 2);

        tcg_temp_free_i32(tmp);

        tmp = load_reg(s, a->rt2);

        neon_store_reg32(tmp, a->vm * 2 + 1);

        tcg_temp_free_i32(tmp);

    }



    return true;

}

target/arm/translate.c

+2 −44
Original line number Diff line number Diff line
@@ -3703,50 +3703,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) 
    case 0xc:

    case 0xd:

        if ((insn & 0x03e00000) == 0x00400000) {

            /* two-register transfer */

            rn = (insn >> 16) & 0xf;

            rd = (insn >> 12) & 0xf;

            if (dp) {

                VFP_DREG_M(rm, insn);

            } else {

                rm = VFP_SREG_M(insn);

            }



            if (insn & ARM_CP_RW_BIT) {

                /* vfp->arm */

                if (dp) {

                    gen_mov_F0_vreg(0, rm * 2);

                    tmp = gen_vfp_mrs();

                    store_reg(s, rd, tmp);

                    gen_mov_F0_vreg(0, rm * 2 + 1);

                    tmp = gen_vfp_mrs();

                    store_reg(s, rn, tmp);

                } else {

                    gen_mov_F0_vreg(0, rm);

                    tmp = gen_vfp_mrs();

                    store_reg(s, rd, tmp);

                    gen_mov_F0_vreg(0, rm + 1);

                    tmp = gen_vfp_mrs();

                    store_reg(s, rn, tmp);

                }

            } else {

                /* arm->vfp */

                if (dp) {

                    tmp = load_reg(s, rd);

                    gen_vfp_msr(tmp);

                    gen_mov_vreg_F0(0, rm * 2);

                    tmp = load_reg(s, rn);

                    gen_vfp_msr(tmp);

                    gen_mov_vreg_F0(0, rm * 2 + 1);

                } else {

                    tmp = load_reg(s, rd);

                    gen_vfp_msr(tmp);

                    gen_mov_vreg_F0(0, rm);

                    tmp = load_reg(s, rn);

                    gen_vfp_msr(tmp);

                    gen_mov_vreg_F0(0, rm + 1);

                }

            }

            /* Already handled by decodetree */

            return 1;

        } else {

            /* Load/store */

            rn = (insn >> 16) & 0xf;

target/arm/vfp.decode

+5 −0
Original line number Diff line number Diff line
@@ -66,3 +66,8 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ 
VMSR_VMRS    ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000

VMOV_single  ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \

             vn=%vn_sp



VMOV_64_sp   ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \

             vm=%vm_sp

VMOV_64_dp   ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \

             vm=%vm_dp