Commit 8110b2bf authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Aleksandar Markovic
Browse files

hw/mips/gt64xxx_pci: Align the pci0-mem size 



One byte is missing, use an aligned size.

    (qemu) info mtree
    memory-region: pci0-mem
      0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem
                                      ^

Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-8-f4bug@amsat.org>
parent ab6bff42

hw/mips/gt64xxx_pci.c

+2 −1
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/units.h"

#include "qemu/log.h"

#include "hw/hw.h"

#include "hw/mips/mips.h"
@@ -1201,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic) 
    dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);

    d = GT64120_PCI_HOST_BRIDGE(dev);

    phb = PCI_HOST_BRIDGE(dev);

    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);

    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);

    address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");

    phb->bus = pci_register_root_bus(dev, "pci",

                                     gt64120_pci_set_irq, gt64120_pci_map_irq,