Commit 8092c6a3 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE integer convert to floating-point 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
[PMM: fixed typo]
Message-id: 20180627043328.11531-6-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 05abe304

target/arm/helper-sve.h

+30 −0
Original line number Diff line number Diff line
@@ -720,6 +720,36 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, 
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)

DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)

DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)

target/arm/sve.decode

+22 −0
Original line number Diff line number Diff line
@@ -133,6 +133,9 @@ 
@rd_pg_rn       ........ esz:2 ... ... ... pg:3 rn:5 rd:5       &rpr_esz

@rd_pg4_pn      ........ esz:2 ... ... .. pg:4 . rn:4 rd:5      &rpr_esz



# One register operand, with governing predicate, no vector element size

@rd_pg_rn_e0    ........ .. ... ... ... pg:3 rn:5 rd:5          &rpr_esz esz=0



# Two register operands with a 6-bit signed immediate.

@rd_rn_i6       ........ ... rn:5 ..... imm:s6 rd:5             &rri
@@ -681,6 +684,25 @@ FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm 
FRECPS          01100101 .. 0 ..... 000 110 ..... .....         @rd_rn_rm

FRSQRTS         01100101 .. 0 ..... 000 111 ..... .....         @rd_rn_rm



### SVE FP Unary Operations Predicated Group



# SVE integer convert to floating-point

SCVTF_hh        01100101 01 010 01 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_sh        01100101 01 010 10 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_dh        01100101 01 010 11 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_ss        01100101 10 010 10 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_sd        01100101 11 010 00 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_ds        01100101 11 010 10 0 101 ... ..... .....        @rd_pg_rn_e0

SCVTF_dd        01100101 11 010 11 0 101 ... ..... .....        @rd_pg_rn_e0



UCVTF_hh        01100101 01 010 01 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_sh        01100101 01 010 10 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_dh        01100101 01 010 11 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_ss        01100101 10 010 10 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_sd        01100101 11 010 00 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_ds        01100101 11 010 10 1 101 ... ..... .....        @rd_pg_rn_e0

UCVTF_dd        01100101 11 010 11 1 101 ... ..... .....        @rd_pg_rn_e0



### SVE Memory - 32-bit Gather and Unsized Contiguous Group



# SVE load predicate register

target/arm/sve_helper.c

+38 −0
Original line number Diff line number Diff line
@@ -2811,6 +2811,44 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) 
    return predtest_ones(d, oprsz, esz_mask);

}



/* Fully general two-operand expander, controlled by a predicate,

 * With the extra float_status parameter.

 */

#define DO_ZPZ_FP(NAME, TYPE, H, OP)                                  \

void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \

{                                                                     \

    intptr_t i = simd_oprsz(desc);                                    \

    uint64_t *g = vg;                                                 \

    do {                                                              \

        uint64_t pg = g[(i - 1) >> 6];                                \

        do {                                                          \

            i -= sizeof(TYPE);                                        \

            if (likely((pg >> (i & 63)) & 1)) {                       \

                TYPE nn = *(TYPE *)(vn + H(i));                       \

                *(TYPE *)(vd + H(i)) = OP(nn, status);                \

            }                                                         \

        } while (i & 63);                                             \

    } while (i != 0);                                                 \

}



DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16)

DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16)

DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32)

DO_ZPZ_FP(sve_scvt_sd, uint64_t,     , int32_to_float64)

DO_ZPZ_FP(sve_scvt_dh, uint64_t,     , int64_to_float16)

DO_ZPZ_FP(sve_scvt_ds, uint64_t,     , int64_to_float32)

DO_ZPZ_FP(sve_scvt_dd, uint64_t,     , int64_to_float64)



DO_ZPZ_FP(sve_ucvt_hh, uint16_t, H1_2, uint16_to_float16)

DO_ZPZ_FP(sve_ucvt_sh, uint32_t, H1_4, uint32_to_float16)

DO_ZPZ_FP(sve_ucvt_ss, uint32_t, H1_4, uint32_to_float32)

DO_ZPZ_FP(sve_ucvt_sd, uint64_t,     , uint32_to_float64)

DO_ZPZ_FP(sve_ucvt_dh, uint64_t,     , uint64_to_float16)

DO_ZPZ_FP(sve_ucvt_ds, uint64_t,     , uint64_to_float32)

DO_ZPZ_FP(sve_ucvt_dd, uint64_t,     , uint64_to_float64)



#undef DO_ZPZ_FP



/*

 * Load contiguous data, protected by a governing predicate.

 */

target/arm/translate-sve.c

+90 −0
Original line number Diff line number Diff line
@@ -3425,6 +3425,96 @@ DO_FP3(FRSQRTS, rsqrts) 


#undef DO_FP3





/*

 *** SVE Floating Point Unary Operations Predicated Group

 */



static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,

                       bool is_fp16, gen_helper_gvec_3_ptr *fn)

{

    if (sve_access_check(s)) {

        unsigned vsz = vec_full_reg_size(s);

        TCGv_ptr status = get_fpstatus_ptr(is_fp16);

        tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),

                           vec_full_reg_offset(s, rn),

                           pred_full_reg_offset(s, pg),

                           status, vsz, vsz, 0, fn);

        tcg_temp_free_ptr(status);

    }

    return true;

}



static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);

}



static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh);

}



static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh);

}



static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss);

}



static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds);

}



static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd);

}



static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd);

}



static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh);

}



static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh);

}



static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh);

}



static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss);

}



static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds);

}



static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd);

}



static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd);

}



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */