Commit 808ebd66 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' into staging 



First RISC-V Patch Set for the 3.1 Soft Freeze

This pull request contains a handful of patches that have been floating
around various trees for a while but haven't made it upstream.  These
patches all appear quite safe.  They're all somewhat independent from
each other:

* One refactors our IRQ management function to allow multiple interrupts
  to be raised an once.  This patch has no functional difference.
* Cleaning up the op_helper/cpu_helper split.  This patch has no
  functional difference.
* Updates to various constants to keep them in sync with the latest ISA
  specification and to remove some non-standard bits that snuck in.
* A fix for a memory leak in the PLIC driver.
* A fix to our device tree handling to avoid provinging a NULL string.

I've given this my standard test: building the port, booting a Fedora
root filesytem on the latest Linux tag, and then shutting down that
image.  Essentially I'm just following the QEMU RISC-V wiki page's
instructions.  Everything looks fine here.

We have a lot more outstanding patches so I'll definately be submitting
another PR for the soft freeze.

# gpg: Signature made Wed 17 Oct 2018 21:17:52 BST
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf0:
  RISC-V: Don't add NULL bootargs to device-tree
  RISC-V: Add missing free for plic_hart_config
  RISC-V: Update CSR and interrupt definitions
  RISC-V: Move non-ops from op_helper to cpu_helper
  RISC-V: Allow setting and clearing multiple irqs

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents a4d71025 7c28f4da

hw/riscv/sifive_clint.c

+4 −4
Original line number Diff line number Diff line
@@ -47,12 +47,12 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value) 
    if (cpu->env.timecmp <= rtc_r) {

        /* if we're setting an MTIMECMP value in the "past",

           immediately raise the timer interrupt */

        riscv_set_local_interrupt(cpu, MIP_MTIP, 1);

        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));

        return;

    }



    /* otherwise, set up the future timer interrupt */

    riscv_set_local_interrupt(cpu, MIP_MTIP, 0);

    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));

    diff = cpu->env.timecmp - rtc_r;

    /* back to ns (note args switched in muldiv64) */

    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
@@ -67,7 +67,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value) 
static void sifive_clint_timer_cb(void *opaque)

{

    RISCVCPU *cpu = opaque;

    riscv_set_local_interrupt(cpu, MIP_MTIP, 1);

    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));

}



/* CPU wants to read rtc or timecmp register */
@@ -132,7 +132,7 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, 
        if (!env) {

            error_report("clint: invalid timecmp hartid: %zu", hartid);

        } else if ((addr & 0x3) == 0) {

            riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MSIP, value != 0);

            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));

        } else {

            error_report("clint: invalid sip write: %08x", (uint32_t)addr);

        }

hw/riscv/sifive_plic.c

+2 −2
Original line number Diff line number Diff line
@@ -142,10 +142,10 @@ static void sifive_plic_update(SiFivePLICState *plic) 
        int level = sifive_plic_irqs_pending(plic, addrid);

        switch (mode) {

        case PLICMode_M:

            riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level);

            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));

            break;

        case PLICMode_S:

            riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_SEIP, level);

            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));

            break;

        default:

            break;

hw/riscv/sifive_u.c

+3 −1
Original line number Diff line number Diff line
@@ -230,7 +230,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 


    qemu_fdt_add_subnode(fdt, "/chosen");

    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);

    if (cmdline) {

        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);

    }

    g_free(nodename);

}

hw/riscv/spike.c

+4 −2
Original line number Diff line number Diff line
@@ -156,9 +156,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 
    g_free(cells);

    g_free(nodename);



    if (cmdline) {

        qemu_fdt_add_subnode(fdt, "/chosen");

        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);

    }

 }



static void spike_v1_10_0_board_init(MachineState *machine)

{

hw/riscv/virt.c

+5 −1
Original line number Diff line number Diff line
@@ -254,7 +254,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 


    qemu_fdt_add_subnode(fdt, "/chosen");

    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);

    if (cmdline) {

        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);

    }

    g_free(nodename);



    return fdt;
@@ -385,6 +387,8 @@ static void riscv_virt_board_init(MachineState *machine) 
    serial_mm_init(system_memory, memmap[VIRT_UART0].base,

        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,

        serial_hd(0), DEVICE_LITTLE_ENDIAN);



    g_free(plic_hart_config);

}



static void riscv_virt_board_machine_init(MachineClass *mc)