Commit 808d77bc authored by Lucien Murray-Pitts's avatar Lucien Murray-Pitts Committed by Laurent Vivier
Browse files

m68k comments break patch submission due to being incorrectly formatted 



Altering all comments in target/m68k to match Qemu coding styles so that future
patches wont fail due to style breaches.

Signed-off-by: default avatarLucien Murray-Pitts <lucienmp.qemu@gmail.com>
Reviewed-by: default avatarLaurent Vivier <laurent@vivier.eu>
Message-Id: <20190606234125.GA4830@localhost.localdomain>
Signed-off-by: default avatarLaurent Vivier <laurent@vivier.eu>
parent bf1fa691

target/m68k/cpu-qom.h

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
#define M68K_CPU_GET_CLASS(obj) \

    OBJECT_GET_CLASS(M68kCPUClass, (obj), TYPE_M68K_CPU)



/**

/*

 * M68kCPUClass:

 * @parent_realize: The parent class' realize handler.

 * @parent_reset: The parent class' reset handler.

target/m68k/cpu.c

+4 −2
Original line number Diff line number Diff line
@@ -203,8 +203,10 @@ static void any_cpu_initfn(Object *obj) 
    m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);

    m68k_set_feature(env, M68K_FEATURE_BRAL);

    m68k_set_feature(env, M68K_FEATURE_CF_FPU);

    /* MAC and EMAC are mututally exclusive, so pick EMAC.

       It's mostly backwards compatible.  */

    /*

     * MAC and EMAC are mututally exclusive, so pick EMAC.

     * It's mostly backwards compatible.

     */

    m68k_set_feature(env, M68K_FEATURE_CF_EMAC);

    m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B);

    m68k_set_feature(env, M68K_FEATURE_USP);

target/m68k/cpu.h

+18 −11
Original line number Diff line number Diff line
@@ -106,9 +106,11 @@ typedef struct CPUM68KState { 
    float_status fp_status;



    uint64_t mactmp;

    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and

       two 8-bit parts.  We store a single 64-bit value and

       rearrange/extend this when changing modes.  */

    /*

     * EMAC Hardware deals with 48-bit values composed of one 32-bit and

     * two 8-bit parts.  We store a single 64-bit value and

     * rearrange/extend this when changing modes.

     */

    uint64_t macc[4];

    uint32_t macsr;

    uint32_t mac_mask;
@@ -146,7 +148,7 @@ typedef struct CPUM68KState { 
    uint32_t features;

} CPUM68KState;



/**

/*

 * M68kCPU:

 * @env: #CPUM68KState

 *
@@ -171,9 +173,11 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 


void m68k_tcg_init(void);

void m68k_cpu_init_gdb(M68kCPU *cpu);

/* you can call this signal handler from your SIGBUS and SIGSEGV

   signal handlers to inform the virtual CPU of exceptions. non zero

   is returned if the signal was handled by the virtual CPU.  */

/*

 * you can call this signal handler from your SIGBUS and SIGSEGV

 * signal handlers to inform the virtual CPU of exceptions. non zero

 * is returned if the signal was handled by the virtual CPU.

 */

int cpu_m68k_signal_handler(int host_signum, void *pinfo,

                           void *puc);

uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
@@ -182,7 +186,8 @@ void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 
void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);





/* Instead of computing the condition codes after each m68k instruction,

/*

 * Instead of computing the condition codes after each m68k instruction,

 * QEMU just stores one operand (called CC_SRC), the result

 * (called CC_DEST) and the type of operation (called CC_OP). When the

 * condition codes are needed, the condition codes can be calculated
@@ -447,9 +452,11 @@ void m68k_switch_sp(CPUM68KState *env); 


void do_m68k_semihosting(CPUM68KState *env, int nr);



/* There are 4 ColdFire core ISA revisions: A, A+, B and C.

   Each feature covers the subset of instructions common to the

   ISA revisions mentioned.  */

/*

 * There are 4 ColdFire core ISA revisions: A, A+, B and C.

 * Each feature covers the subset of instructions common to the

 * ISA revisions mentioned.

 */



enum m68k_features {

    M68K_FEATURE_M68000,

target/m68k/fpu_helper.c

+4 −2
Original line number Diff line number Diff line
@@ -25,7 +25,8 @@ 
#include "exec/cpu_ldst.h"

#include "softfloat.h"



/* Undefined offsets may be different on various FPU.

/*

 * Undefined offsets may be different on various FPU.

 * On 68040 they return 0.0 (floatx80_zero)

 */
@@ -611,7 +612,8 @@ void HELPER(fcos)(CPUM68KState *env, FPReg *res, FPReg *val) 
void HELPER(fsincos)(CPUM68KState *env, FPReg *res0, FPReg *res1, FPReg *val)

{

    floatx80 a = val->d;

    /* If res0 and res1 specify the same floating-point data register,

    /*

     * If res0 and res1 specify the same floating-point data register,

     * the sine result is stored in the register, and the cosine

     * result is discarded.

     */

target/m68k/gdbstub.c

+4 −2
Original line number Diff line number Diff line
@@ -41,8 +41,10 @@ int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 
            return gdb_get_reg32(mem_buf, env->pc);

        }

    }

    /* FP registers not included here because they vary between

       ColdFire and m68k.  Use XML bits for these.  */

    /*

     * FP registers not included here because they vary between

     * ColdFire and m68k.  Use XML bits for these.

     */

    return 0;

}