Commit 7faae0b3 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160906-1' into staging 



target-arm queue:
 * fix incorrect LPAE bit in FSR for alignment faults
 * ACPI: fix the AML ID format for CPU devices to work for
   large numbers of CPUs
 * ast2400: add memory controller device model
 * m25p80: fix the vmstate structure name (migration break)

# gpg: Signature made Tue 06 Sep 2016 20:02:28 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160906-1:
  block: m25p80: Fix vmstate structure name
  ARM: ACPI: fix the AML ID format for CPU devices
  target-arm: Fix lpae bit in FSR on an alignment fault
  ast2400: add a memory controller device model

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 2926375c c827c06a

hw/arm/ast2400.c

+15 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define AST2400_FMC_BASE         0X1E620000

#define AST2400_SPI_BASE         0X1E630000

#define AST2400_VIC_BASE         0x1E6C0000

#define AST2400_SDMC_BASE        0x1E6E0000

#define AST2400_SCU_BASE         0x1E6E2000

#define AST2400_TIMER_BASE       0x1E782000

#define AST2400_I2C_BASE         0x1E78A000
@@ -97,6 +98,12 @@ static void ast2400_init(Object *obj) 
    object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi");

    object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL);

    qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default());



    object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);

    object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);

    qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());

    qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",

                         AST2400_A0_SILICON_REV);

}



static void ast2400_realize(DeviceState *dev, Error **errp)
@@ -183,6 +190,14 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);



    /* SDMC - SDRAM Memory Controller */

    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, AST2400_SDMC_BASE);

}



static void ast2400_class_init(ObjectClass *oc, void *data)

hw/arm/virt-acpi-build.c

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) 
    uint16_t i;



    for (i = 0; i < smp_cpus; i++) {

        Aml *dev = aml_device("C%03x", i);

        Aml *dev = aml_device("C%.03X", i);

        aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));

        aml_append(dev, aml_name_decl("_UID", aml_int(i)));

        aml_append(scope, dev);

hw/block/m25p80.c

+14 −15
Original line number Diff line number Diff line
@@ -1189,9 +1189,9 @@ static Property m25p80_properties[] = { 
};



static const VMStateDescription vmstate_m25p80 = {

    .name = "xilinx_spi",

    .version_id = 3,

    .minimum_version_id = 1,

    .name = "m25p80",

    .version_id = 0,

    .minimum_version_id = 0,

    .pre_save = m25p80_pre_save,

    .fields = (VMStateField[]) {

        VMSTATE_UINT8(state, Flash),
@@ -1200,20 +1200,19 @@ static const VMStateDescription vmstate_m25p80 = { 
        VMSTATE_UINT32(pos, Flash),

        VMSTATE_UINT8(needed_bytes, Flash),

        VMSTATE_UINT8(cmd_in_progress, Flash),

        VMSTATE_UNUSED(4),

        VMSTATE_UINT32(cur_addr, Flash),

        VMSTATE_BOOL(write_enable, Flash),

        VMSTATE_BOOL_V(reset_enable, Flash, 2),

        VMSTATE_UINT8_V(ear, Flash, 2),

        VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),

        VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),

        VMSTATE_UINT32_V(volatile_cfg, Flash, 2),

        VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),

        VMSTATE_BOOL_V(quad_enable, Flash, 3),

        VMSTATE_UINT8_V(spansion_cr1nv, Flash, 3),

        VMSTATE_UINT8_V(spansion_cr2nv, Flash, 3),

        VMSTATE_UINT8_V(spansion_cr3nv, Flash, 3),

        VMSTATE_UINT8_V(spansion_cr4nv, Flash, 3),

        VMSTATE_BOOL(reset_enable, Flash),

        VMSTATE_UINT8(ear, Flash),

        VMSTATE_BOOL(four_bytes_address_mode, Flash),

        VMSTATE_UINT32(nonvolatile_cfg, Flash),

        VMSTATE_UINT32(volatile_cfg, Flash),

        VMSTATE_UINT32(enh_volatile_cfg, Flash),

        VMSTATE_BOOL(quad_enable, Flash),

        VMSTATE_UINT8(spansion_cr1nv, Flash),

        VMSTATE_UINT8(spansion_cr2nv, Flash),

        VMSTATE_UINT8(spansion_cr3nv, Flash),

        VMSTATE_UINT8(spansion_cr4nv, Flash),

        VMSTATE_END_OF_LIST()

    }

};

hw/misc/Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -52,4 +52,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o 
obj-$(CONFIG_EDU) += edu.o

obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o

obj-$(CONFIG_AUX) += auxbus.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
 
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o

hw/misc/aspeed_sdmc.c

0 → 100644
+263 −0
Original line number Diff line number Diff line 
/*

 * ASPEED SDRAM Memory Controller

 *

 * Copyright (C) 2016 IBM Corp.

 *

 * This code is licensed under the GPL version 2 or later.  See

 * the COPYING file in the top-level directory.

 */



#include "qemu/osdep.h"

#include "qemu/log.h"

#include "hw/misc/aspeed_sdmc.h"

#include "hw/misc/aspeed_scu.h"

#include "hw/qdev-properties.h"

#include "qapi/error.h"

#include "trace.h"



/* Protection Key Register */

#define R_PROT            (0x00 / 4)

#define   PROT_KEY_UNLOCK     0xFC600309



/* Configuration Register */

#define R_CONF            (0x04 / 4)



/*

 * Configuration register Ox4 (for Aspeed AST2400 SOC)

 *

 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is

 * what we care about right now as it is checked by U-Boot to

 * determine the RAM size.

 */



#define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */

#define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)

#define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)

#define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)

#define ASPEED_SDMC_ECC_ENABLE          (1 << 7)

#define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */

#define ASPEED_SDMC_DRAM_BANK           (1 << 5)

#define ASPEED_SDMC_DRAM_BURST          (1 << 4)

#define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */

#define     ASPEED_SDMC_VGA_8MB             0x0

#define     ASPEED_SDMC_VGA_16MB            0x1

#define     ASPEED_SDMC_VGA_32MB            0x2

#define     ASPEED_SDMC_VGA_64MB            0x3

#define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)

#define     ASPEED_SDMC_DRAM_64MB           0x0

#define     ASPEED_SDMC_DRAM_128MB          0x1

#define     ASPEED_SDMC_DRAM_256MB          0x2

#define     ASPEED_SDMC_DRAM_512MB          0x3



#define ASPEED_SDMC_READONLY_MASK                       \

    (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \

     ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))

/*

 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)

 *

 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION

 * should be set to 1 for the AST2500 SOC.

 */

#define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */

#define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)

#define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */

#define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */

#define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)

#define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)

#define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)

#define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */

#define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */



/* DRAM size definitions differs */

#define     ASPEED_SDMC_AST2500_128MB       0x0

#define     ASPEED_SDMC_AST2500_256MB       0x1

#define     ASPEED_SDMC_AST2500_512MB       0x2

#define     ASPEED_SDMC_AST2500_1024MB      0x3



#define ASPEED_SDMC_AST2500_READONLY_MASK                               \

    (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \

     ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \

     ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))



static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)

{

    AspeedSDMCState *s = ASPEED_SDMC(opaque);



    addr >>= 2;



    if (addr >= ARRAY_SIZE(s->regs)) {

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",

                      __func__, addr);

        return 0;

    }



    return s->regs[addr];

}



static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,

                             unsigned int size)

{

    AspeedSDMCState *s = ASPEED_SDMC(opaque);



    addr >>= 2;



    if (addr >= ARRAY_SIZE(s->regs)) {

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",

                      __func__, addr);

        return;

    }



    if (addr != R_PROT && s->regs[R_PROT] != PROT_KEY_UNLOCK) {

        qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);

        return;

    }



    if (addr == R_CONF) {

        /* Make sure readonly bits are kept */

        switch (s->silicon_rev) {

        case AST2400_A0_SILICON_REV:

            data &= ~ASPEED_SDMC_READONLY_MASK;

            break;

        case AST2500_A0_SILICON_REV:

            data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;

            break;

        default:

            g_assert_not_reached();

        }

    }



    s->regs[addr] = data;

}



static const MemoryRegionOps aspeed_sdmc_ops = {

    .read = aspeed_sdmc_read,

    .write = aspeed_sdmc_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .valid.min_access_size = 4,

    .valid.max_access_size = 4,

};



static int ast2400_rambits(void)

{

    switch (ram_size >> 20) {

    case 64:

        return ASPEED_SDMC_DRAM_64MB;

    case 128:

        return ASPEED_SDMC_DRAM_128MB;

    case 256:

        return ASPEED_SDMC_DRAM_256MB;

    case 512:

        return ASPEED_SDMC_DRAM_512MB;

    default:

        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid RAM size: 0x"

                      RAM_ADDR_FMT "\n", __func__, ram_size);

        break;

    }



    /* set a minimum default */

    return ASPEED_SDMC_DRAM_64MB;

}



static int ast2500_rambits(void)

{

    switch (ram_size >> 20) {

    case 128:

        return ASPEED_SDMC_AST2500_128MB;

    case 256:

        return ASPEED_SDMC_AST2500_256MB;

    case 512:

        return ASPEED_SDMC_AST2500_512MB;

    case 1024:

        return ASPEED_SDMC_AST2500_1024MB;

    default:

        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid RAM size: 0x"

                      RAM_ADDR_FMT "\n", __func__, ram_size);

        break;

    }



    /* set a minimum default */

    return ASPEED_SDMC_AST2500_128MB;

}



static void aspeed_sdmc_reset(DeviceState *dev)

{

    AspeedSDMCState *s = ASPEED_SDMC(dev);



    memset(s->regs, 0, sizeof(s->regs));



    /* Set ram size bit and defaults values */

    switch (s->silicon_rev) {

    case AST2400_A0_SILICON_REV:

        s->regs[R_CONF] |=

            ASPEED_SDMC_VGA_COMPAT |

            ASPEED_SDMC_DRAM_SIZE(ast2400_rambits());

        break;



    case AST2500_A0_SILICON_REV:

        s->regs[R_CONF] |=

            ASPEED_SDMC_HW_VERSION(1) |

            ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |

            ASPEED_SDMC_DRAM_SIZE(ast2500_rambits());

        break;



    default:

        g_assert_not_reached();

    }

}



static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    AspeedSDMCState *s = ASPEED_SDMC(dev);



    if (!is_supported_silicon_rev(s->silicon_rev)) {

        error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,

                s->silicon_rev);

        return;

    }



    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,

                          TYPE_ASPEED_SDMC, 0x1000);

    sysbus_init_mmio(sbd, &s->iomem);

}



static const VMStateDescription vmstate_aspeed_sdmc = {

    .name = "aspeed.sdmc",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),

        VMSTATE_END_OF_LIST()

    }

};



static Property aspeed_sdmc_properties[] = {

    DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),

    DEFINE_PROP_END_OF_LIST(),

};



static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = aspeed_sdmc_realize;

    dc->reset = aspeed_sdmc_reset;

    dc->desc = "ASPEED SDRAM Memory Controller";

    dc->vmsd = &vmstate_aspeed_sdmc;

    dc->props = aspeed_sdmc_properties;

}



static const TypeInfo aspeed_sdmc_info = {

    .name = TYPE_ASPEED_SDMC,

    .parent = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(AspeedSDMCState),

    .class_init = aspeed_sdmc_class_init,

};



static void aspeed_sdmc_register_types(void)

{

    type_register_static(&aspeed_sdmc_info);

}



type_init(aspeed_sdmc_register_types);