Commit 7faa66aa authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

target-microblaze: Introduce a use-barrel property 



Introduce a use-barrel property making barrel shifter instructions
optional.

Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent d79fcbc2

target/microblaze/cpu.c

+5 −4
Original line number Diff line number Diff line
@@ -150,8 +150,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    qemu_init_vcpu(cs);



    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \

                       | PVR0_USE_DIV_MASK \

    env->pvr.regs[0] = PVR0_USE_DIV_MASK \

                       | PVR0_USE_HW_MUL_MASK \

                       | PVR0_USE_EXC_MASK \

                       | PVR0_USE_ICACHE_MASK \
@@ -162,7 +161,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
                        | PVR2_I_LMB_MASK \

                        | PVR2_USE_MSR_INSTR \

                        | PVR2_USE_PCMP_INSTR \

                        | PVR2_USE_BARREL_MASK \

                        | PVR2_USE_DIV_MASK \

                        | PVR2_USE_HW_MUL_MASK \

                        | PVR2_USE_MUL64_MASK \
@@ -182,13 +180,15 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |

                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |

                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |

                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |

                        (version_code << PVR0_VERSION_SHIFT) |

                        (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);



    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);

                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |

                        (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0);



    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?

                                        PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -235,6 +235,7 @@ static Property mb_properties[] = { 
     *                  are enabled

     */

    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),

    DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),

    DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),

    DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,

                     false),

target/microblaze/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -298,6 +298,7 @@ struct MicroBlazeCPU { 
        bool stackprot;

        uint32_t base_vectors;

        uint8_t use_fpu;

        bool use_barrel;

        bool use_mmu;

        bool dcache_writeback;

        bool endi;

target/microblaze/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -665,7 +665,7 @@ static void dec_barrel(DisasContext *dc) 


    if ((dc->tb_flags & MSR_EE_FLAG)

          && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)

          && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_BARREL_MASK)) {

          && !dc->cpu->cfg.use_barrel) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(dc, EXCP_HW_EXCP);

        return;