Commit 7ebd5f2e authored by Sergey Fedorov's avatar Sergey Fedorov Committed by Peter Maydell
Browse files

target-arm: rename c1_coproc to cpacr_el1 



Rename the field holding CPACR_EL1 system register state in AArch64
naming style.

Signed-off-by: default avatarSergey Fedorov <serge.fdrv@gmail.com>
[PMM: also fixed a couple of missed occurrences in cpu.c]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ef7bab8d

hw/arm/pxa2xx.c

+1 −1
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 
        s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;

        s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;

        s->cpu->env.cp15.sctlr_ns = 0;

        s->cpu->env.cp15.c1_coproc = 0;

        s->cpu->env.cp15.cpacr_el1 = 0;

        s->cpu->env.cp15.ttbr0_el[1] = 0;

        s->cpu->env.cp15.dacr_ns = 0;

        s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */

target-arm/cpu.c

+2 −2
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static void arm_cpu_reset(CPUState *s) 
        /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */

        env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;

        /* and to the FP/Neon instructions */

        env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);

        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);

#else

        /* Reset into the highest available EL */

        if (arm_feature(env, ARM_FEATURE_EL3)) {
@@ -126,7 +126,7 @@ static void arm_cpu_reset(CPUState *s) 
    } else {

#if defined(CONFIG_USER_ONLY)

        /* Userspace expects access to cp10 and cp11 for FP/Neon */

        env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);

        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);

#endif

    }

target-arm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ typedef struct CPUARMState { 
            };

            uint64_t sctlr_el[4];

        };

        uint64_t c1_coproc; /* Coprocessor access register.  */

        uint64_t cpacr_el1; /* Architectural feature access control register */

        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */

        uint64_t sder; /* Secure debug enable register. */

        uint32_t nsacr; /* Non-secure access control register. */
@@ -1813,7 +1813,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 
    int fpen;



    if (arm_feature(env, ARM_FEATURE_V6)) {

        fpen = extract32(env->cp15.c1_coproc, 20, 2);

        fpen = extract32(env->cp15.cpacr_el1, 20, 2);

    } else {

        /* CPACR doesn't exist before v6, so VFP is always accessible */

        fpen = 3;

target-arm/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -589,7 +589,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
        }

        value &= mask;

    }

    env->cp15.c1_coproc = value;

    env->cp15.cpacr_el1 = value;

}



static const ARMCPRegInfo v6_cp_reginfo[] = {
@@ -615,7 +615,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { 
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },

    { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,

      .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,

      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),

      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),

      .resetvalue = 0, .writefn = cpacr_write },

    REGINFO_SENTINEL

};