Commit 7ea32024 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-june-01-2020' into staging 



MIPS queue for June 1st, 2020

# gpg: Signature made Mon 01 Jun 2020 12:29:25 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-june-01-2020:
  hw/mips: fuloong2e: Set preferred page size to 16KB
  target/mips: Support variable page size
  target/mips: Add more CP0 register for save/restore
  hw/mips: Add CPU IRQ3 delivery for KVM
  configure: Add KVM target support for MIPS64
  tests/Makefile: Fix description of "make check"

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents b73f417a a08d60bc

configure

+1 −1
Original line number Diff line number Diff line
@@ -198,7 +198,7 @@ supported_kvm_target() { 
        arm:arm | aarch64:aarch64 | \

        i386:i386 | i386:x86_64 | i386:x32 | \

        x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \

        mips:mips | mipsel:mips | \

        mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \

        ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \

        s390x:s390x)

            return 0

hw/mips/fuloong2e.c

+1 −0
Original line number Diff line number Diff line
@@ -392,6 +392,7 @@ static void mips_fuloong2e_machine_init(MachineClass *mc) 
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");

    mc->default_ram_size = 256 * MiB;

    mc->default_ram_id = "fuloong2e.ram";

    mc->minimum_page_bits = 14;

}



DEFINE_MACHINE("fuloong2e", mips_fuloong2e_machine_init)

hw/mips/mips_int.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) 
        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));

    }



    if (kvm_enabled() && irq == 2) {

    if (kvm_enabled() && (irq == 2 || irq == 3)) {

        kvm_mips_set_interrupt(cpu, irq, level);

    }

target/mips/cpu-param.h

+5 −0
Original line number Diff line number Diff line
@@ -23,7 +23,12 @@ 
#  define TARGET_VIRT_ADDR_SPACE_BITS 32

#endif

#endif

#ifdef CONFIG_USER_ONLY

#define TARGET_PAGE_BITS 12

#else

#define TARGET_PAGE_BITS_VARY

#define TARGET_PAGE_BITS_MIN 12

#endif

#define NB_MMU_MODES 4



#endif

target/mips/kvm.c

+212 −0
Original line number Diff line number Diff line
@@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 
    (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))



#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)

#define KVM_REG_MIPS_CP0_RANDOM         MIPS_CP0_32(1, 0)

#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)

#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)

#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)

#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)

#define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)

#define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)

#define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)

#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)

#define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)

#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)

#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)

#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
@@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 
#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)

#define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)

#define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)

#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)

#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)

#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)

#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)

#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)

#define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)

#define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)

#define KVM_REG_MIPS_CP0_CONFIG6        MIPS_CP0_32(16, 6)

#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)

#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)

#define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)

#define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)

#define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)

#define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)

#define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)

#define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)



static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,

                                       int32_t *addr)
@@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 
                                         (1U << CP0C5_UFE) | \

                                         (1U << CP0C5_FRE) | \

                                         (1U << CP0C5_UFR))

#define KVM_REG_MIPS_CP0_CONFIG6_MASK   ((1U << CP0C6_BPPASS) | \

                                         (0x3fU << CP0C6_KPOS) | \

                                         (1U << CP0C6_KE) | \

                                         (1U << CP0C6_VTLBONLY) | \

                                         (1U << CP0C6_LASX) | \

                                         (1U << CP0C6_SSEN) | \

                                         (1U << CP0C6_DISDRTIME) | \

                                         (1U << CP0C6_PIXNUEN) | \

                                         (1U << CP0C6_SCRAND) | \

                                         (1U << CP0C6_LLEXCEN) | \

                                         (1U << CP0C6_DISVC) | \

                                         (1U << CP0C6_VCLRU) | \

                                         (1U << CP0C6_DCLRU) | \

                                         (1U << CP0C6_PIXUEN) | \

                                         (1U << CP0C6_DISBLKLYEN) | \

                                         (1U << CP0C6_UMEMUALEN) | \

                                         (1U << CP0C6_SFBEN) | \

                                         (1U << CP0C6_FLTINT) | \

                                         (1U << CP0C6_VLTINT) | \

                                         (1U << CP0C6_DISBTB) | \

                                         (3U << CP0C6_STPREFCTL) | \

                                         (1U << CP0C6_INSTPREF) | \

                                         (1U << CP0C6_DATAPREF))



static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,

                                          int32_t *addr, int32_t mask)
@@ -729,6 +767,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 
        DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,

                                 &env->CP0_Context);

    if (err < 0) {
@@ -747,11 +790,40 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 
        DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN,

                               &env->CP0_PageGrain);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE,

                               &env->CP0_PWBase);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD,

                               &env->CP0_PWField);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE,

                               &env->CP0_PWSize);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
@@ -799,6 +871,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 
        DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG,

                                  &env->CP0_Config0,

                                  KVM_REG_MIPS_CP0_CONFIG_MASK);
@@ -841,12 +918,61 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 
        DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6,

                                  &env->CP0_Config6,

                                  KVM_REG_MIPS_CP0_CONFIG6_MASK);

    if (err < 0) {

        DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT,

                                 &env->CP0_XContext);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,

                                 &env->CP0_ErrorEPC);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1,

                                 &env->CP0_KScratch[0]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2,

                                 &env->CP0_KScratch[1]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3,

                                 &env->CP0_KScratch[2]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4,

                                 &env->CP0_KScratch[3]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5,

                                 &env->CP0_KScratch[4]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6,

                                 &env->CP0_KScratch[5]);

    if (err < 0) {

        DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err);

        ret = err;

    }



    return ret;

}
@@ -862,6 +988,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) 
        DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,

                                 &env->CP0_Context);

    if (err < 0) {
@@ -880,11 +1011,40 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) 
        DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN,

                               &env->CP0_PageGrain);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE,

                               &env->CP0_PWBase);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD,

                               &env->CP0_PWField);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE,

                               &env->CP0_PWSize);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
@@ -932,6 +1092,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) 
        DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err);
@@ -962,12 +1127,59 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) 
        DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT,

                                 &env->CP0_XContext);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,

                                 &env->CP0_ErrorEPC);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1,

                                 &env->CP0_KScratch[0]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2,

                                 &env->CP0_KScratch[1]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3,

                                 &env->CP0_KScratch[2]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4,

                                 &env->CP0_KScratch[3]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5,

                                 &env->CP0_KScratch[4]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err);

        ret = err;

    }

    err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6,

                                 &env->CP0_KScratch[5]);

    if (err < 0) {

        DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err);

        ret = err;

    }



    return ret;

}