Commit 7de9729f authored by Richard Henderson's avatar Richard Henderson
Browse files

target/openrisc: Start conversion to decodetree.py 



Begin with the 0x08 major opcode, the system instructions.

Acked-by: default avatarStafford Horne <shorne@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 4e2d3007

target/openrisc/Makefile.objs

+9 −0
Original line number Diff line number Diff line
@@ -3,3 +3,12 @@ obj-y += cpu.o exception.o interrupt.o mmu.o translate.o 
obj-y += exception_helper.o fpu_helper.o \

         interrupt_helper.o mmu_helper.o sys_helper.o

obj-y += gdbstub.o



DECODETREE = $(SRC_PATH)/scripts/decodetree.py



target/openrisc/decode.inc.c: \

  $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)

	$(call quiet-command,\

	  $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)



target/openrisc/translate.o: target/openrisc/decode.inc.c

target/openrisc/insns.decode

0 → 100644
+28 −0
Original line number Diff line number Diff line 
#

# OpenRISC instruction decode definitions.

#

# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>

#

# This library is free software; you can redistribute it and/or

# modify it under the terms of the GNU Lesser General Public

# License as published by the Free Software Foundation; either

# version 2 of the License, or (at your option) any later version.

#

# This library is distributed in the hope that it will be useful,

# but WITHOUT ANY WARRANTY; without even the implied warranty of

# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

# Lesser General Public License for more details.

#

# You should have received a copy of the GNU Lesser General Public

# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#



####

# System Instructions

####



l_sys           001000 0000000000 k:16

l_trap          001000 0100000000 k:16

l_msync         001000 1000000000 00000000 00000000

l_psync         001000 1010000000 00000000 00000000

l_csync         001000 1100000000 00000000 00000000

target/openrisc/translate.c

+41 −43
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 


#include "exec/helper-proto.h"

#include "exec/helper-gen.h"

#include "exec/gen-icount.h"



#include "trace-tcg.h"

#include "exec/log.h"
@@ -51,6 +52,9 @@ typedef struct DisasContext { 
    uint32_t delayed_branch;

} DisasContext;



/* Include the auto-generated decoder.  */

#include "decode.inc.c"



static TCGv cpu_sr;

static TCGv cpu_R[32];

static TCGv cpu_R0;
@@ -65,7 +69,6 @@ static TCGv cpu_lock_value; 
static TCGv_i32 fpcsr;

static TCGv_i64 cpu_mac;        /* MACHI:MACLO */

static TCGv_i32 cpu_dflag;

#include "exec/gen-icount.h"



void openrisc_translate_init(void)

{
@@ -1241,46 +1244,41 @@ static void dec_compi(DisasContext *dc, uint32_t insn) 
    }

}



static void dec_sys(DisasContext *dc, uint32_t insn)

static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)

{

    uint32_t op0;

    uint32_t K16;



    op0 = extract32(insn, 16, 10);

    K16 = extract32(insn, 0, 16);



    switch (op0) {

    case 0x000:    /* l.sys */

        LOG_DIS("l.sys %d\n", K16);

    LOG_DIS("l.sys %d\n", a->k);

    tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);

    gen_exception(dc, EXCP_SYSCALL);

    dc->base.is_jmp = DISAS_NORETURN;

        break;

    return true;

}



    case 0x100:    /* l.trap */

        LOG_DIS("l.trap %d\n", K16);

static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)

{

    LOG_DIS("l.trap %d\n", a->k);

    tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);

    gen_exception(dc, EXCP_TRAP);

    dc->base.is_jmp = DISAS_NORETURN;

        break;



    case 0x300:    /* l.csync */

        LOG_DIS("l.csync\n");

        break;

    return true;

}



    case 0x200:    /* l.msync */

static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn)

{

    LOG_DIS("l.msync\n");

    tcg_gen_mb(TCG_MO_ALL);

        break;

    return true;

}



    case 0x270:    /* l.psync */

static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn)

{

    LOG_DIS("l.psync\n");

        break;



    default:

        gen_illegal_exception(dc);

        break;

    return true;

}



static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)

{

    LOG_DIS("l.csync\n");

    return true;

}



static void dec_float(DisasContext *dc, uint32_t insn)
@@ -1506,19 +1504,19 @@ static void dec_float(DisasContext *dc, uint32_t insn) 
static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)

{

    uint32_t op0;

    uint32_t insn;

    insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);

    op0 = extract32(insn, 26, 6);

    uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);



    /* Transition to the auto-generated decoder.  */

    if (decode(dc, insn)) {

        return;

    }



    op0 = extract32(insn, 26, 6);

    switch (op0) {

    case 0x06:

        dec_M(dc, insn);

        break;



    case 0x08:

        dec_sys(dc, insn);

        break;



    case 0x2e:

        dec_logic(dc, insn);

        break;