Commit 7d56239f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' into staging 



target-arm queue:
 * microbit: Add the UART to our nRF51 SoC model
 * Add a virtual Xilinx Versal board "xlnx-versal-virt"
 * hw/arm/virt: Set VIRT_COMPAT_3_0 compat
 * MAINTAINERS: Remove bouncing email in ARM ACPI
 * strongarm: mask off high[31:28] bits from dir and state registers
 * target/arm: Conditionalize some asserts on aarch32 support
 * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro

# gpg: Signature made Fri 02 Nov 2018 17:14:43 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181102:
  hw/arm: versal: Add a virtual Xilinx Versal board
  hw/arm: versal: Add a model of Xilinx Versal SoC
  target/arm: Conditionalize some asserts on aarch32 support
  hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
  strongarm: mask off high[31:28] bits from dir and state registers
  MAINTAINERS: Remove bouncing email in ARM ACPI
  tests/boot-serial-test: Add microbit board testcase
  hw/arm/nrf51_soc: Connect UART to nRF51 SoC
  hw/char: Implement nRF51 SoC UART
  hw/arm/virt: Set VIRT_COMPAT_3_0 compat

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 69e2d038 6f16da53

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -627,7 +627,6 @@ F: hw/*/xlnx*.c 
F: include/hw/*/xlnx*.h



ARM ACPI Subsystem

M: Shannon Zhao <zhaoshenglong@huawei.com>

M: Shannon Zhao <shannon.zhaosl@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

default-configs/aarch64-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -8,4 +8,5 @@ CONFIG_DDC=y 
CONFIG_DPCD=y

CONFIG_XLNX_ZYNQMP=y

CONFIG_XLNX_ZYNQMP_ARM=y

CONFIG_XLNX_VERSAL=y

CONFIG_ARM_SMMUV3=y

hw/arm/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o 
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o

obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o

obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o

obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o

obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o

obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

hw/arm/microbit.c

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "qapi/error.h"

#include "hw/boards.h"

#include "hw/arm/arm.h"

#include "sysemu/sysemu.h"

#include "exec/address-spaces.h"



#include "hw/arm/nrf51_soc.h"
@@ -35,6 +36,7 @@ static void microbit_init(MachineState *machine) 


    sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),

                          TYPE_NRF51_SOC);

    qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));

    object_property_set_link(soc, OBJECT(system_memory), "memory",

                             &error_fatal);

    object_property_set_bool(soc, true, "realized", &error_fatal);

hw/arm/nrf51_soc.c

+20 −0
Original line number Diff line number Diff line
@@ -43,9 +43,12 @@ 
#define NRF51822_FLASH_SIZE     (256 * 1024)

#define NRF51822_SRAM_SIZE      (16 * 1024)



#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)



static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)

{

    NRF51State *s = NRF51_SOC(dev_soc);

    MemoryRegion *mr;

    Error *err = NULL;



    if (!s->board_memory) {
@@ -82,6 +85,18 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 
    }

    memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);



    /* UART */

    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);

    memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,

                       qdev_get_gpio_in(DEVICE(&s->cpu),

                       BASE_TO_IRQ(UART_BASE)));



    create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);

    create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);

    create_unimplemented_device("nrf51_soc.private",
@@ -99,6 +114,11 @@ static void nrf51_soc_init(Object *obj) 
    qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",

                         ARM_CPU_TYPE_NAME("cortex-m0"));

    qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);



    sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),

                           TYPE_NRF51_UART);

    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",

                              &error_abort);

}



static Property nrf51_soc_properties[] = {