Commit 7cff8988 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec 



For immediate rotate , we can implement this in two instructions,
using SLI.  For variable rotate, the oddness of aarch64 right-shift-
as-negative-left-shift means a backend-specific expansion works best.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 885b1706

tcg/aarch64/tcg-target.inc.c

+51 −2
Original line number Diff line number Diff line
@@ -557,6 +557,7 @@ typedef enum { 
    I3614_SSHR      = 0x0f000400,

    I3614_SSRA      = 0x0f001400,

    I3614_SHL       = 0x0f005400,

    I3614_SLI       = 0x2f005400,

    I3614_USHR      = 0x2f000400,

    I3614_USRA      = 0x2f001400,
@@ -2411,6 +2412,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_sari_vec:

        tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);

        break;

    case INDEX_op_aa64_sli_vec:

        tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));

        break;

    case INDEX_op_shlv_vec:

        tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);

        break;
@@ -2498,8 +2502,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 
    case INDEX_op_shlv_vec:

    case INDEX_op_bitsel_vec:

        return 1;

    case INDEX_op_rotli_vec:

    case INDEX_op_shrv_vec:

    case INDEX_op_sarv_vec:

    case INDEX_op_rotlv_vec:

    case INDEX_op_rotrv_vec:

        return -1;

    case INDEX_op_mul_vec:

    case INDEX_op_smax_vec:
@@ -2517,14 +2524,24 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 
                       TCGArg a0, ...)

{

    va_list va;

    TCGv_vec v0, v1, v2, t1;

    TCGv_vec v0, v1, v2, t1, t2;

    TCGArg a2;



    va_start(va, a0);

    v0 = temp_tcgv_vec(arg_temp(a0));

    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));

    v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));

    a2 = va_arg(va, TCGArg);

    v2 = temp_tcgv_vec(arg_temp(a2));



    switch (opc) {

    case INDEX_op_rotli_vec:

        t1 = tcg_temp_new_vec(type);

        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));

        vec_gen_4(INDEX_op_aa64_sli_vec, type, vece,

                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);

        tcg_temp_free_vec(t1);

        break;



    case INDEX_op_shrv_vec:

    case INDEX_op_sarv_vec:

        /* Right shifts are negative left shifts for AArch64.  */
@@ -2537,6 +2554,35 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 
        tcg_temp_free_vec(t1);

        break;



    case INDEX_op_rotlv_vec:

        t1 = tcg_temp_new_vec(type);

        tcg_gen_dupi_vec(vece, t1, 8 << vece);

        tcg_gen_sub_vec(vece, t1, v2, t1);

        /* Right shifts are negative left shifts for AArch64.  */

        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),

                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));

        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),

                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));

        tcg_gen_or_vec(vece, v0, v0, t1);

        tcg_temp_free_vec(t1);

        break;



    case INDEX_op_rotrv_vec:

        t1 = tcg_temp_new_vec(type);

        t2 = tcg_temp_new_vec(type);

        tcg_gen_neg_vec(vece, t1, v2);

        tcg_gen_dupi_vec(vece, t2, 8 << vece);

        tcg_gen_add_vec(vece, t2, t1, t2);

        /* Right shifts are negative left shifts for AArch64.  */

        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),

                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));

        vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t2),

                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));

        tcg_gen_or_vec(vece, v0, t1, t2);

        tcg_temp_free_vec(t1);

        tcg_temp_free_vec(t2);

        break;



    default:

        g_assert_not_reached();

    }
@@ -2557,6 +2603,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 
    static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };

    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };

    static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };

    static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };

    static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };

    static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };

    static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
@@ -2751,6 +2798,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 
        return &w_w_wZ;

    case INDEX_op_bitsel_vec:

        return &w_w_w_w;

    case INDEX_op_aa64_sli_vec:

        return &w_0_w;



    default:

        return NULL;

tcg/aarch64/tcg-target.opc.h

+1 −0
Original line number Diff line number Diff line
@@ -12,3 +12,4 @@ 
 */



DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)

DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC)