Commit 7bc8f973 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191025' into staging 



target-arm queue:
 * raspi boards: some cleanup
 * raspi: implement the bcm2835 system timer device
 * raspi: implement a dummy thermal sensor
 * misc devices: switch to ptimer transaction API
 * cache TB flag state to improve performance of cpu_get_tb_cpu_state
 * aspeed: Add an AST2600 eval board

# gpg: Signature made Fri 25 Oct 2019 13:11:25 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191025: (42 commits)
  hw/arm/highbank: Use AddressSpace when using write_secondary_boot()
  hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot
  hw/arm/bcm2836: Rename cpus[] as cpu[].core
  hw/arm/bcm2836: Make the SoC code modular
  hw/arm/bcm2835_peripherals: Use the SYS_timer
  hw/timer/bcm2835: Add the BCM2835 SYS_timer
  hw/arm/bcm2835_peripherals: Use the thermal sensor block
  hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor
  hw/watchdog/milkymist-sysctl.c: Switch to transaction-based ptimer API
  hw/m68k/mcf5206.c: Switch to transaction-based ptimer API
  hw/timer/grlib_gptimer.c: Switch to transaction-based ptimer API
  hw/timer/slavio_timer.c: Switch to transaction-based ptimer API
  hw/timer/slavio_timer: Remove useless check for NULL t->timer
  hw/dma/xilinx_axidma.c: Switch to transaction-based ptimer API
  hw/timer/xilinx_timer.c: Switch to transaction-based ptimer API
  hw/net/fsl_etsec/etsec.c: Switch to transaction-based ptimer API
  target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
  linux-user/arm: Rebuild hflags for TARGET_WORDS_BIGENDIAN
  linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN
  target/arm: Rebuild hflags for M-profile NVIC
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 58560ad2 f9469c1a

hw/arm/aspeed.c

+23 −0
Original line number Diff line number Diff line
@@ -88,6 +88,10 @@ struct AspeedBoardState { 
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */

#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1



/* AST2600 evb hardware value */

#define AST2600_EVB_HW_STRAP1 0x000000C0

#define AST2600_EVB_HW_STRAP2 0x00000003



/*

 * The max ram region is for firmwares that scan the address space

 * with load/store to guess how much RAM the SoC has.
@@ -187,6 +191,8 @@ static void aspeed_board_init(MachineState *machine, 
                             &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",

                            &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2",

                            &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",

                            &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
@@ -308,6 +314,12 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 
    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);

}



static void ast2600_evb_i2c_init(AspeedBoardState *bmc)

{

    /* Start with some devices on our I2C busses */

    ast2500_evb_i2c_init(bmc);

}



static void romulus_bmc_i2c_init(AspeedBoardState *bmc)

{

    AspeedSoCState *soc = &bmc->soc;
@@ -455,6 +467,17 @@ static const AspeedBoardConfig aspeed_boards[] = { 
        .num_cs    = 2,

        .i2c_init  = witherspoon_bmc_i2c_init,

        .ram       = 512 * MiB,

    }, {

        .name      = MACHINE_TYPE_NAME("ast2600-evb"),

        .desc      = "Aspeed AST2600 EVB (Cortex A7)",

        .soc_name  = "ast2600-a0",

        .hw_strap1 = AST2600_EVB_HW_STRAP1,

        .hw_strap2 = AST2600_EVB_HW_STRAP2,

        .fmc_model = "w25q512jv",

        .spi_model = "mx66u51235f",

        .num_cs    = 1,

        .i2c_init  = ast2600_evb_i2c_init,

        .ram       = 1 * GiB,

    },

};

hw/arm/bcm2835_peripherals.c

+29 −1
Original line number Diff line number Diff line
@@ -58,6 +58,10 @@ static void bcm2835_peripherals_init(Object *obj) 
    /* Interrupt Controller */

    sysbus_init_child_obj(obj, "ic", &s->ic, sizeof(s->ic), TYPE_BCM2835_IC);



    /* SYS Timer */

    sysbus_init_child_obj(obj, "systimer", &s->systmr, sizeof(s->systmr),

                          TYPE_BCM2835_SYSTIMER);



    /* UART0 */

    sysbus_init_child_obj(obj, "uart0", &s->uart0, sizeof(s->uart0),

                          TYPE_PL011);
@@ -111,6 +115,10 @@ static void bcm2835_peripherals_init(Object *obj) 
    object_property_add_const_link(OBJECT(&s->dma), "dma-mr",

                                   OBJECT(&s->gpu_bus_mr), &error_abort);



    /* Thermal */

    sysbus_init_child_obj(obj, "thermal", &s->thermal, sizeof(s->thermal),

                          TYPE_BCM2835_THERMAL);



    /* GPIO */

    sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),

                          TYPE_BCM2835_GPIO);
@@ -167,6 +175,18 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));

    sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));



    /* Sys Timer */

    object_property_set_bool(OBJECT(&s->systmr), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(&s->peri_mr, ST_OFFSET,

                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0,

        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,

                               INTERRUPT_ARM_TIMER));



    /* UART0 */

    qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));

    object_property_set_bool(OBJECT(&s->uart0), true, "realized", &err);
@@ -321,6 +341,15 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
                                                  INTERRUPT_DMA0 + n));

    }



    /* THERMAL */

    object_property_set_bool(OBJECT(&s->thermal), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    memory_region_add_subregion(&s->peri_mr, THERMAL_OFFSET,

                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0));



    /* GPIO */

    object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);

    if (err) {
@@ -339,7 +368,6 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    }



    create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);

    create_unimp(s, &s->systmr, "bcm2835-systimer", ST_OFFSET, 0x20);

    create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);

    create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);

    create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);

hw/arm/bcm2836.c

+23 −21
Original line number Diff line number Diff line
@@ -16,15 +16,11 @@ 
#include "hw/arm/raspi_platform.h"

#include "hw/sysbus.h"



/* Peripheral base address seen by the CPU */

#define BCM2836_PERI_BASE       0x3F000000



/* "QA7" (Pi2) interrupt controller and mailboxes etc. */

#define BCM2836_CONTROL_BASE    0x40000000



struct BCM283XInfo {

    const char *name;

    const char *cpu_type;

    hwaddr peri_base; /* Peripheral base address seen by the CPU */

    hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */

    int clusterid;

};
@@ -32,12 +28,16 @@ static const BCM283XInfo bcm283x_socs[] = { 
    {

        .name = TYPE_BCM2836,

        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),

        .peri_base = 0x3f000000,

        .ctrl_base = 0x40000000,

        .clusterid = 0xf,

    },

#ifdef TARGET_AARCH64

    {

        .name = TYPE_BCM2837,

        .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),

        .peri_base = 0x3f000000,

        .ctrl_base = 0x40000000,

        .clusterid = 0x0,

    },

#endif
@@ -51,8 +51,9 @@ static void bcm2836_init(Object *obj) 
    int n;



    for (n = 0; n < BCM283X_NCPUS; n++) {

        object_initialize_child(obj, "cpu[*]", &s->cpus[n], sizeof(s->cpus[n]),

                                info->cpu_type, &error_abort, NULL);

        object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,

                                sizeof(s->cpu[n].core), info->cpu_type,

                                &error_abort, NULL);

    }



    sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control),
@@ -104,7 +105,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 
    }



    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,

                            BCM2836_PERI_BASE, 1);

                            info->peri_base, 1);



    /* bcm2836 interrupt controller (and mailboxes, etc.) */

    object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
@@ -113,7 +114,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 
        return;

    }



    sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, BCM2836_CONTROL_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);



    sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,

        qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
@@ -122,11 +123,11 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 


    for (n = 0; n < BCM283X_NCPUS; n++) {

        /* TODO: this should be converted to a property of ARM_CPU */

        s->cpus[n].mp_affinity = (info->clusterid << 8) | n;

        s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;



        /* set periphbase/CBAR value for CPU-local registers */

        object_property_set_int(OBJECT(&s->cpus[n]),

                                BCM2836_PERI_BASE + MSYNC_OFFSET,

        object_property_set_int(OBJECT(&s->cpu[n].core),

                                info->peri_base,

                                "reset-cbar", &err);

        if (err) {

            error_propagate(errp, err);
@@ -134,14 +135,15 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 
        }



        /* start powered off if not enabled */

        object_property_set_bool(OBJECT(&s->cpus[n]), n >= s->enabled_cpus,

        object_property_set_bool(OBJECT(&s->cpu[n].core), n >= s->enabled_cpus,

                                 "start-powered-off", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }



        object_property_set_bool(OBJECT(&s->cpus[n]), true, "realized", &err);

        object_property_set_bool(OBJECT(&s->cpu[n].core), true,

                                 "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;
@@ -149,18 +151,18 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 


        /* Connect irq/fiq outputs from the interrupt controller. */

        qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n,

                qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_IRQ));

                qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ));

        qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n,

                qdev_get_gpio_in(DEVICE(&s->cpus[n]), ARM_CPU_FIQ));

                qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ));



        /* Connect timers from the CPU to the interrupt controller */

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_PHYS,

        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_VIRT,

        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_HYP,

        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_SEC,

        qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));

    }

}

hw/arm/highbank.c

+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {

        smpboot[n] = tswap32(smpboot[n]);

    }

    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);

    rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR,

                          arm_boot_address_space(cpu, info));

}



static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)

hw/arm/raspi.c

+8 −6
Original line number Diff line number Diff line
@@ -60,12 +60,14 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 
    QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0

                      || (BOARDSETUP_ADDR >> 4) >= 0x100);



    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),

                       info->smp_loader_start);

    rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),

                          info->smp_loader_start,

                          arm_boot_address_space(cpu, info));

}



static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)

{

    AddressSpace *as = arm_boot_address_space(cpu, info);

    /* Unlike the AArch32 version we don't need to call the board setup hook.

     * The mechanism for doing the spin-table is also entirely different.

     * We must have four 64-bit fields at absolute addresses
@@ -92,10 +94,10 @@ static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 
        0, 0, 0, 0

    };



    rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot),

                       info->smp_loader_start);

    rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables),

                       SPINTABLE_ADDR);

    rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),

                          info->smp_loader_start, as);

    rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),

                          SPINTABLE_ADDR, as);

}



static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)