Commit 7b9c09f7 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/sstabellini/tags/xen-2015-09-10-tag' into staging 



xen-2015-09-10

# gpg: Signature made Thu 10 Sep 2015 17:52:08 BST using RSA key ID 70E1AE90
# gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>"

* remotes/sstabellini/tags/xen-2015-09-10-tag: (29 commits)
  xen/pt: Don't slurp wholesale the PCI configuration registers
  xen/pt: Check for return values for xen_host_pci_[get|set] in init
  xen/pt: Move bulk of xen_pt_unregister_device in its own routine.
  xen/pt: Make xen_pt_unregister_device idempotent
  xen/pt: Log xen_host_pci_get/set errors in MSI code.
  xen/pt: Log xen_host_pci_get in two init functions
  xen/pt: Remove XenPTReg->data field.
  xen/pt: Check if reg->init function sets the 'data' past the reg->size
  xen/pt: Sync up the dev.config and data values.
  xen/pt: Use xen_host_pci_get_[byte|word] instead of dev.config
  xen/pt: Use XEN_PT_LOG properly to guard against compiler warnings.
  xen/pt/msi: Add the register value when printing logging and error messages
  xen: use errno instead of rc for xc_domain_add_to_physmap
  xen/pt: xen_host_pci_config_read returns -errno, not -1 on failure
  xen/pt: Make xen_pt_msi_set_enable static
  xen/pt: Update comments with proper function name.
  xen/HVM: atomically access pointers in bufioreq handling
  xen-hvm: When using xc_domain_add_to_physmap also include errno when reporting
  xen, gfx passthrough: add opregion mapping
  xen, gfx passthrough: register host bridge specific to passthrough
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents fe556410 cae99f1d

configure

+28 −0
Original line number Diff line number Diff line
@@ -1881,6 +1881,34 @@ EOF 
#if !defined(HVM_MAX_VCPUS)

# error HVM_MAX_VCPUS not defined

#endif

int main(void) {

  xc_interface *xc;

  xs_daemon_open();

  xc = xc_interface_open(0, 0, 0);

  xc_hvm_set_mem_type(0, 0, HVMMEM_ram_ro, 0, 0);

  xc_gnttab_open(NULL, 0);

  xc_domain_add_to_physmap(0, 0, XENMAPSPACE_gmfn, 0, 0);

  xc_hvm_inject_msi(xc, 0, 0xf0000000, 0x00000000);

  xc_hvm_create_ioreq_server(xc, 0, HVM_IOREQSRV_BUFIOREQ_ATOMIC, NULL);

  xc_reserved_device_memory_map(xc, 0, 0, 0, 0, NULL, 0);

  return 0;

}

EOF

      compile_prog "" "$xen_libs"

    then

    xen_ctrl_version=460

    xen=yes



  # Xen 4.5

  elif

      cat > $TMPC <<EOF &&

#include <xenctrl.h>

#include <xenstore.h>

#include <stdint.h>

#include <xen/hvm/hvm_info_table.h>

#if !defined(HVM_MAX_VCPUS)

# error HVM_MAX_VCPUS not defined

#endif

int main(void) {

  xc_interface *xc;

  xs_daemon_open();

hw/core/machine.c

+20 −0
Original line number Diff line number Diff line
@@ -226,6 +226,20 @@ static void machine_set_usb(Object *obj, bool value, Error **errp) 
    ms->usb_disabled = !value;

}



static bool machine_get_igd_gfx_passthru(Object *obj, Error **errp)

{

    MachineState *ms = MACHINE(obj);



    return ms->igd_gfx_passthru;

}



static void machine_set_igd_gfx_passthru(Object *obj, bool value, Error **errp)

{

    MachineState *ms = MACHINE(obj);



    ms->igd_gfx_passthru = value;

}



static char *machine_get_firmware(Object *obj, Error **errp)

{

    MachineState *ms = MACHINE(obj);
@@ -388,6 +402,12 @@ static void machine_initfn(Object *obj) 
    object_property_set_description(obj, "usb",

                                    "Set on/off to enable/disable usb",

                                    NULL);

    object_property_add_bool(obj, "igd-passthru",

                             machine_get_igd_gfx_passthru,

                             machine_set_igd_gfx_passthru, NULL);

    object_property_set_description(obj, "igd-passthru",

                                    "Set on/off to enable/disable igd passthrou",

                                    NULL);

    object_property_add_str(obj, "firmware",

                            machine_get_firmware,

                            machine_set_firmware, NULL);

hw/i386/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ obj-$(CONFIG_XEN) += ../xenpv/ xen/ 


obj-y += kvmvapic.o

obj-y += acpi-build.o

obj-y += pci-assign-load-rom.o



gen-hex-y += hw/i386/acpi-dsdt.hex

gen-hex-y += hw/i386/q35-acpi-dsdt.hex

hw/i386/kvm/pci-assign.c

+7 −75
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include "hw/pci/pci.h"

#include "hw/pci/msi.h"

#include "kvm_i386.h"

#include "hw/pci/pci-assign.h"



#define MSIX_PAGE_SIZE 0x1000
@@ -48,17 +49,6 @@ 
#define IORESOURCE_PREFETCH 0x00002000  /* No side effects */

#define IORESOURCE_MEM_64   0x00100000



//#define DEVICE_ASSIGNMENT_DEBUG



#ifdef DEVICE_ASSIGNMENT_DEBUG

#define DEBUG(fmt, ...)                                       \

    do {                                                      \

        fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);  \

    } while (0)

#else

#define DEBUG(fmt, ...)

#endif



typedef struct PCIRegion {

    int type;           /* Memory or port I/O */

    int valid;
@@ -1896,73 +1886,15 @@ static void assign_register_types(void) 


type_init(assign_register_types)



/*

 * Scan the assigned devices for the devices that have an option ROM, and then

 * load the corresponding ROM data to RAM. If an error occurs while loading an

 * option ROM, we just ignore that option ROM and continue with the next one.

 */

static void assigned_dev_load_option_rom(AssignedDevice *dev)

{

    char name[32], rom_file[64];

    FILE *fp;

    uint8_t val;

    struct stat st;

    void *ptr;



    /* If loading ROM from file, pci handles it */

    if (dev->dev.romfile || !dev->dev.rom_bar) {

        return;

    }

    int size = 0;



    snprintf(rom_file, sizeof(rom_file),

             "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom",

             dev->host.domain, dev->host.bus, dev->host.slot,

             dev->host.function);

    pci_assign_dev_load_option_rom(&dev->dev, OBJECT(dev), &size,

                                   dev->host.domain, dev->host.bus,

                                   dev->host.slot, dev->host.function);



    if (stat(rom_file, &st)) {

        return;

    }



    if (access(rom_file, F_OK)) {

        error_report("pci-assign: Insufficient privileges for %s", rom_file);

        return;

    }



    /* Write "1" to the ROM file to enable it */

    fp = fopen(rom_file, "r+");

    if (fp == NULL) {

        return;

    if (!size) {

        error_report("pci-assign: Invalid ROM.");

    }

    val = 1;

    if (fwrite(&val, 1, 1, fp) != 1) {

        goto close_rom;

    }

    fseek(fp, 0, SEEK_SET);



    snprintf(name, sizeof(name), "%s.rom",

            object_get_typename(OBJECT(dev)));

    memory_region_init_ram(&dev->dev.rom, OBJECT(dev), name, st.st_size,

                           &error_abort);

    vmstate_register_ram(&dev->dev.rom, &dev->dev.qdev);

    ptr = memory_region_get_ram_ptr(&dev->dev.rom);

    memset(ptr, 0xff, st.st_size);



    if (!fread(ptr, 1, st.st_size, fp)) {

        error_report("pci-assign: Cannot read from host %s", rom_file);

        error_printf("Device option ROM contents are probably invalid "

                     "(check dmesg).\nSkip option ROM probe with rombar=0, "

                     "or load from file with romfile=\n");

        goto close_rom;

    }



    pci_register_bar(&dev->dev, PCI_ROM_SLOT, 0, &dev->dev.rom);

    dev->dev.has_rom = true;

close_rom:

    /* Write "0" to disable ROM */

    fseek(fp, 0, SEEK_SET);

    val = 0;

    if (!fwrite(&val, 1, 1, fp)) {

        DEBUG("%s\n", "Failed to disable pci-sysfs rom file");

    }

    fclose(fp);

}

hw/i386/pc_piix.c

+133 −6
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
#include "qemu/error-report.h"

#ifdef CONFIG_XEN

#include <xen/hvm/hvm_info_table.h>

#include "hw/xen/xen_pt.h"

#endif

#include "migration/migration.h"
@@ -76,7 +77,8 @@ static bool has_reserved_memory = true; 
static bool kvmclock_enabled = true;



/* PC hardware initialisation */

static void pc_init1(MachineState *machine)

static void pc_init1(MachineState *machine,

                     const char *host_type, const char *pci_type)

{

    PCMachineState *pcms = PC_MACHINE(machine);

    MemoryRegion *system_memory = get_system_memory();
@@ -194,7 +196,9 @@ static void pc_init1(MachineState *machine) 
    }



    if (pci_enabled) {

        pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,

        pci_bus = i440fx_init(host_type,

                              pci_type,

                              &i440fx_state, &piix3_devfn, &isa_bus, gsi,

                              system_memory, system_io, machine->ram_size,

                              pcms->below_4g_mem_size,

                              pcms->above_4g_mem_size,
@@ -412,15 +416,25 @@ static void pc_init_isa(MachineState *machine) 
    }

    x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, 1 << KVM_FEATURE_PV_EOI);

    enable_compat_apic_id_mode();

    pc_init1(machine);

    pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, TYPE_I440FX_PCI_DEVICE);

}



#ifdef CONFIG_XEN

static void pc_xen_hvm_init_pci(MachineState *machine)

{

    const char *pci_type = has_igd_gfx_passthru ?

                TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE : TYPE_I440FX_PCI_DEVICE;



    pc_init1(machine,

             TYPE_I440FX_PCI_HOST_BRIDGE,

             pci_type);

}



static void pc_xen_hvm_init(MachineState *machine)

{

    PCIBus *bus;



    pc_init1(machine);

    pc_xen_hvm_init_pci(machine);



    bus = pci_find_primary_bus();

    if (bus != NULL) {
@@ -436,7 +450,8 @@ static void pc_xen_hvm_init(MachineState *machine) 
        if (compat) { \

            compat(machine); \

        } \

        pc_init1(machine); \

        pc_init1(machine, TYPE_I440FX_PCI_HOST_BRIDGE, \

                 TYPE_I440FX_PCI_DEVICE); \

    } \

    DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
@@ -878,6 +893,118 @@ static void pc_i440fx_0_10_machine_options(MachineClass *m) 
DEFINE_I440FX_MACHINE(v0_10, "pc-0.10", pc_compat_0_13,

                      pc_i440fx_0_10_machine_options);



typedef struct {

    uint16_t gpu_device_id;

    uint16_t pch_device_id;

    uint8_t pch_revision_id;

} IGDDeviceIDInfo;



/* In real world different GPU should have different PCH. But actually

 * the different PCH DIDs likely map to different PCH SKUs. We do the

 * same thing for the GPU. For PCH, the different SKUs are going to be

 * all the same silicon design and implementation, just different

 * features turn on and off with fuses. The SW interfaces should be

 * consistent across all SKUs in a given family (eg LPT). But just same

 * features may not be supported.

 *

 * Most of these different PCH features probably don't matter to the

 * Gfx driver, but obviously any difference in display port connections

 * will so it should be fine with any PCH in case of passthrough.

 *

 * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)

 * scenarios, 0x9cc3 for BDW(Broadwell).

 */

static const IGDDeviceIDInfo igd_combo_id_infos[] = {

    /* HSW Classic */

    {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */

    {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */

    {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */

    {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */

    {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */

    /* HSW ULT */

    {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */

    {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */

    {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */

    {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */

    {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */

    {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */

    /* HSW CRW */

    {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */

    {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */

    /* HSW Server */

    {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */

    /* HSW SRVR */

    {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */

    /* BSW */

    {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */

    {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */

    {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */

    {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */

    {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */

    {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */

    {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */

    {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */

    {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */

    {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */

    {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */

};



static void isa_bridge_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);



    dc->desc        = "ISA bridge faked to support IGD PT";

    k->vendor_id    = PCI_VENDOR_ID_INTEL;

    k->class_id     = PCI_CLASS_BRIDGE_ISA;

};



static TypeInfo isa_bridge_info = {

    .name          = "igd-passthrough-isa-bridge",

    .parent        = TYPE_PCI_DEVICE,

    .instance_size = sizeof(PCIDevice),

    .class_init = isa_bridge_class_init,

};



static void pt_graphics_register_types(void)

{

    type_register_static(&isa_bridge_info);

}

type_init(pt_graphics_register_types)



void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id)

{

    struct PCIDevice *bridge_dev;

    int i, num;

    uint16_t pch_dev_id = 0xffff;

    uint8_t pch_rev_id;



    num = ARRAY_SIZE(igd_combo_id_infos);

    for (i = 0; i < num; i++) {

        if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) {

            pch_dev_id = igd_combo_id_infos[i].pch_device_id;

            pch_rev_id = igd_combo_id_infos[i].pch_revision_id;

        }

    }



    if (pch_dev_id == 0xffff) {

        return;

    }



    /* Currently IGD drivers always need to access PCH by 1f.0. */

    bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),

                                   "igd-passthrough-isa-bridge");



    /*

     * Note that vendor id is always PCI_VENDOR_ID_INTEL.

     */

    if (!bridge_dev) {

        fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n");

        return;

    }

    pci_config_set_device_id(bridge_dev->config, pch_dev_id);

    pci_config_set_revision(bridge_dev->config, pch_rev_id);

}



static void isapc_machine_options(MachineClass *m)

{