Loading configure +1 −0 Original line number Diff line number Diff line Loading @@ -6555,6 +6555,7 @@ case "$target_name" in cris) ;; hppa) mttcg="yes" ;; lm32) ;; Loading target/hppa/cpu.h +6 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have a weak memory model, but with TLB bits that force ordering on a per-page basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" Loading Loading
configure +1 −0 Original line number Diff line number Diff line Loading @@ -6555,6 +6555,7 @@ case "$target_name" in cris) ;; hppa) mttcg="yes" ;; lm32) ;; Loading
target/hppa/cpu.h +6 −0 Original line number Diff line number Diff line Loading @@ -42,6 +42,12 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have a weak memory model, but with TLB bits that force ordering on a per-page basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL #define CPUArchState struct CPUHPPAState #include "exec/cpu-defs.h" Loading