Commit 7ab7e9c7 authored by Alistair Francis's avatar Alistair Francis Committed by Richard Henderson
Browse files

tcg/riscv: Fix RISC-VH host build failure 



Commit 269bd5d8 "cpu: Move the softmmu tlb to CPUNegativeOffsetState'
broke the RISC-V host build as there are two variables that are used but
not defined.

This patch renames the undefined variables mask_off and table_off to the
existing (but unused) mask_ofs and table_ofs variables.

Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-Id: <79729cc88ca509e08b5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent f34edbc7

tcg/riscv/tcg-target.inc.c

+2 −2
Original line number Diff line number Diff line
@@ -980,8 +980,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, 
    int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);

    TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;



    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off);

    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off);

    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs);

    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs);



    tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl,

                    TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);