Commit 7a5853ce authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



virtio, pci, pc: fixes, cleanups, features

Bugfixes, cleanups all over the place.
Ability to disable hotplug for pci express ports.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Sun 08 Mar 2020 13:27:54 GMT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  hw/i386/intel_iommu: Simplify vtd_find_as_from_bus_num() logic
  vhost-vsock: fix error message output
  vhost: correctly turn on VIRTIO_F_IOMMU_PLATFORM
  pcie_root_port: Add hotplug disabling option

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 67f17e23 a6f65f4f

hw/i386/intel_iommu.c

+17 −15
Original line number Diff line number Diff line
@@ -987,14 +987,17 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) 
static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)

{

    VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];

    if (!vtd_bus) {

    GHashTableIter iter;



    if (vtd_bus) {

        return vtd_bus;

    }



    /*

     * Iterate over the registered buses to find the one which

         * currently hold this bus number, and update the bus_num

         * lookup table:

     * currently holds this bus number and update the bus_num

     * lookup table.

     */

        GHashTableIter iter;



    g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);

    while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {

        if (pci_bus_num(vtd_bus->bus) == bus_num) {
@@ -1002,9 +1005,8 @@ static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num) 
            return vtd_bus;

        }

    }

        vtd_bus = NULL;

    }

    return vtd_bus;



    return NULL;

}



/* Given the @iova, get relevant @slptep. @slpte_level will be the last level

hw/pci-bridge/pcie_root_port.c

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ static void rp_realize(PCIDevice *d, Error **errp) 


    pcie_cap_arifwd_init(d);

    pcie_cap_deverr_init(d);

    pcie_cap_slot_init(d, s->slot);

    pcie_cap_slot_init(d, s);

    pcie_cap_root_init(d);



    pcie_chassis_create(s->chassis);

hw/pci-bridge/xio3130_downstream.c

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) 
    }

    pcie_cap_flr_init(d);

    pcie_cap_deverr_init(d);

    pcie_cap_slot_init(d, s->slot);

    pcie_cap_slot_init(d, s);

    pcie_cap_arifwd_init(d);



    pcie_chassis_create(s->chassis);

hw/pci/pcie.c

+7 −4
Original line number Diff line number Diff line
@@ -495,7 +495,7 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, 


/* pci express slot for pci express root/downstream port

   PCI express capability slot registers */

void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)

void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)

{

    uint32_t pos = dev->exp.exp_cap;
@@ -505,13 +505,16 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 
    pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,

                                 ~PCI_EXP_SLTCAP_PSN);

    pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,

                               (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |

                               (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |

                               PCI_EXP_SLTCAP_EIP |

                               PCI_EXP_SLTCAP_HPS |

                               PCI_EXP_SLTCAP_HPC |

                               PCI_EXP_SLTCAP_PIP |

                               PCI_EXP_SLTCAP_AIP |

                               PCI_EXP_SLTCAP_ABP);

    if (s->hotplug) {

        pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,

                                   PCI_EXP_SLTCAP_HPS |

                                   PCI_EXP_SLTCAP_HPC);

    }



    if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {

        pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,

hw/pci/pcie_port.c

+1 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ static const TypeInfo pcie_port_type_info = { 
static Property pcie_slot_props[] = {

    DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),

    DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),

    DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true),

    DEFINE_PROP_END_OF_LIST()

};