Unverified Commit 79f86934 authored by Michael Clark's avatar Michael Clark
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RISC-V: Update E and I extension order 



Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I are mutually exclusive, as the E extension
will be added to the RISC-V port in the future.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 8d196c43

target/riscv/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 


/* RISC-V CPU definitions */



static const char riscv_exts[26] = "IMAFDQECLBJTPVNSUHKORWXYZG";

static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";



const char * const riscv_int_regnames[] = {

  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ 
#define RV(x) ((target_ulong)1 << (x - 'A'))



#define RVI RV('I')

#define RVE RV('E') /* E and I are mutually exclusive */

#define RVM RV('M')

#define RVA RV('A')

#define RVF RV('F')