Commit 79cf9fad authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151103' into staging 



target-arm queue:
 * code cleanup to use symbolic constants for register bank numbers
 * fix direct booting of modern Linux kernels on xilinx_zynq by setting
   SCLR values to what the kernel expects firmware to have done
 * implement SYSRESETREQ for ARMv7M CPU (stellaris boards)
 * update MAINTAINERS to mention new qemu-arm mailing list
 * clean up display of PSTATE in AArch64 debug logs
 * report Secure/Nonsecure status in CPU debug logs
 * fix a missing _CCA attribute in ACPI tables
 * add support for GICv3 to ACPI tables

# gpg: Signature made Tue 03 Nov 2015 13:58:46 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20151103:
  ARM: ACPI: Fix MPIDR value in ACPI table
  hw/arm/virt-acpi-build: Add GICC ACPI subtable for GICv3
  hw/arm/virt-acpi-build: _CCA attribute is compulsory
  target-arm: Report S/NS status in the CPU debug logs
  target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32
  MAINTAINERS: Add new qemu-arm mailing list to ARM related entries
  arm: stellaris: exit on external reset request
  armv7-m: Implement SYSRESETREQ
  armv7-m: Return DeviceState* from armv7m_init()
  arm: xilinx_zynq: Add linux pre-boot
  arm: boot: Add board specific setup code API
  arm: boot: Adjust indentation of FIXUP comments
  target-arm: Add and use symbolic names for register banks

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 19bb5467 5d9c1756

MAINTAINERS

+23 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ F: disas/alpha.c 


ARM

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: target-arm/

F: hw/arm/
@@ -216,6 +217,7 @@ F: */kvm.* 


ARM

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: target-arm/kvm.c
@@ -287,6 +289,7 @@ ARM Machines 
------------

Allwinner-a10

M: Beniamino Galvani <b.galvani@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/*/allwinner*

F: include/hw/*/allwinner*
@@ -294,6 +297,7 @@ F: hw/arm/cubieboard.c 


ARM PrimeCell

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/char/pl011.c

F: hw/display/pl110*
@@ -308,6 +312,7 @@ F: include/hw/arm/primecell.h 


ARM cores

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/intc/arm*

F: hw/intc/gic_internal.h
@@ -327,54 +332,64 @@ M: Evgeny Voevodin <e.voevodin@samsung.com> 
M: Maksim Kozlov <m.kozlov@samsung.com>

M: Igor Mitsyanko <i.mitsyanko@gmail.com>

M: Dmitry Solodkiy <d.solodkiy@samsung.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/*/exynos*



Calxeda Highbank

M: Rob Herring <robh@kernel.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/highbank.c

F: hw/net/xgmac.c



Canon DIGIC

M: Antony Pavlov <antonynpavlov@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: include/hw/arm/digic.h

F: hw/*/digic*



Gumstix

L: qemu-devel@nongnu.org

L: qemu-arm@nongnu.org

S: Orphan

F: hw/arm/gumstix.c



i.MX31

M: Peter Chubb <peter.chubb@nicta.com.au>

L: qemu-arm@nongnu.org

S: Odd fixes

F: hw/*/imx*

F: hw/arm/kzm.c



Integrator CP

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/integratorcp.c



Musicpal

M: Jan Kiszka <jan.kiszka@web.de>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/musicpal.c



nSeries

M: Andrzej Zaborowski <balrogg@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/nseries.c



Palm

M: Andrzej Zaborowski <balrogg@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/palm.c



Real View

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/realview*

F: hw/intc/realview_gic.c
@@ -382,6 +397,7 @@ F: include/hw/intc/realview_gic.h 


PXA2XX

M: Andrzej Zaborowski <balrogg@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/mainstone.c

F: hw/arm/spitz.c
@@ -391,17 +407,20 @@ F: hw/*/pxa2xx* 


Stellaris

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/*/stellaris*



Versatile PB

M: Peter Maydell <peter.maydell@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/*/versatile*



Xilinx Zynq

M: Alistair Francis <alistair.francis@xilinx.com>

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/xilinx_zynq.c

F: hw/misc/zynq_slcr.c
@@ -411,6 +430,7 @@ F: hw/ssi/xilinx_spips.c 
Xilinx ZynqMP

M: Alistair Francis <alistair.francis@xilinx.com>

M: Peter Crosthwaite <crosthwaite.peter@gmail.com>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/xlnx-zynqmp.c

F: hw/arm/xlnx-ep108.c
@@ -419,6 +439,7 @@ F: include/hw/arm/xlnx-zynqmp.h 
ARM ACPI Subsystem

M: Shannon Zhao <zhaoshenglong@huawei.com>

M: Shannon Zhao <shannon.zhao@linaro.org>

L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/virt-acpi-build.c

F: include/hw/arm/virt-acpi-build.h
@@ -1235,6 +1256,7 @@ AArch64 target 
M: Claudio Fontana <claudio.fontana@huawei.com>

M: Claudio Fontana <claudio.fontana@gmail.com>

S: Maintained

L: qemu-arm@nongnu.org

F: tcg/aarch64/

F: disas/arm-a64.cc

F: disas/libvixl/
@@ -1242,6 +1264,7 @@ F: disas/libvixl/ 
ARM target

M: Andrzej Zaborowski <balrogg@gmail.com>

S: Maintained

L: qemu-arm@nongnu.org

F: tcg/arm/

F: disas/arm.c

hw/arm/armv7m.c

+2 −7
Original line number Diff line number Diff line
@@ -166,17 +166,15 @@ static void armv7m_reset(void *opaque) 
   mem_size is in bytes.

   Returns the NVIC array.  */



qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,

DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,

                      const char *kernel_filename, const char *cpu_model)

{

    ARMCPU *cpu;

    CPUARMState *env;

    DeviceState *nvic;

    qemu_irq *pic = g_new(qemu_irq, num_irq);

    int image_size;

    uint64_t entry;

    uint64_t lowaddr;

    int i;

    int big_endian;

    MemoryRegion *hack = g_new(MemoryRegion, 1);
@@ -198,9 +196,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 
    qdev_init_nofail(nvic);

    sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,

                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));

    for (i = 0; i < num_irq; i++) {

        pic[i] = qdev_get_gpio_in(nvic, i);

    }



#ifdef TARGET_WORDS_BIGENDIAN

    big_endian = 1;
@@ -234,7 +229,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, 
    memory_region_add_subregion(system_memory, 0xfffff000, hack);



    qemu_register_reset(armv7m_reset, cpu);

    return pic;

    return nvic;

}



static Property bitband_properties[] = {

hw/arm/boot.c

+27 −9
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ typedef enum { 
    FIXUP_NONE = 0,     /* do nothing */

    FIXUP_TERMINATOR,   /* end of insns */

    FIXUP_BOARDID,      /* overwrite with board ID number */

    FIXUP_BOARD_SETUP,  /* overwrite with board specific setup code address */

    FIXUP_ARGPTR,       /* overwrite with pointer to kernel args */

    FIXUP_ENTRYPOINT,   /* overwrite with kernel entry point */

    FIXUP_GIC_CPU_IF,   /* overwrite with GIC CPU interface address */
@@ -58,8 +59,17 @@ static const ARMInsnFixup bootloader_aarch64[] = { 
    { 0, FIXUP_TERMINATOR }

};



/* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */

/* A very small bootloader: call the board-setup code (if needed),

 * set r0-r2, then jump to the kernel.

 * If we're not calling boot setup code then we don't copy across

 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.

 */



static const ARMInsnFixup bootloader[] = {

    { 0xe28fe008 }, /* add     lr, pc, #8 */

    { 0xe51ff004 }, /* ldr     pc, [pc, #-4] */

    { 0, FIXUP_BOARD_SETUP },

#define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3

    { 0xe3a00000 }, /* mov     r0, #0 */

    { 0xe59f1004 }, /* ldr     r1, [pc, #4] */

    { 0xe59f2004 }, /* ldr     r2, [pc, #4] */
@@ -131,6 +141,7 @@ static void write_bootloader(const char *name, hwaddr addr, 
        case FIXUP_NONE:

            break;

        case FIXUP_BOARDID:

        case FIXUP_BOARD_SETUP:

        case FIXUP_ARGPTR:

        case FIXUP_ENTRYPOINT:

        case FIXUP_GIC_CPU_IF:
@@ -640,6 +651,9 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) 
        elf_machine = EM_AARCH64;

    } else {

        primary_loader = bootloader;

        if (!info->write_board_setup) {

            primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;

        }

        kernel_load_offset = KERNEL_LOAD_ADDR;

        elf_machine = EM_ARM;

    }
@@ -745,6 +759,7 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) 
        info->initrd_size = initrd_size;



        fixupcontext[FIXUP_BOARDID] = info->board_id;

        fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;



        /* for device tree boot, we pass the DTB directly in r2. Otherwise

         * we point to the kernel args.
@@ -793,6 +808,9 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) 
        if (info->nb_cpus > 1) {

            info->write_secondary_boot(cpu, info);

        }

        if (info->write_board_setup) {

            info->write_board_setup(cpu, info);

        }



        /* Notify devices which need to fake up firmware initialization

         * that we're doing a direct kernel boot.

hw/arm/stellaris.c

+30 −11
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "net/net.h"

#include "hw/boards.h"

#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"



#define GPIO_A 0

#define GPIO_B 1
@@ -1176,6 +1177,14 @@ static int stellaris_adc_init(SysBusDevice *sbd) 
    return 0;

}



static

void do_sys_reset(void *opaque, int n, int level)

{

    if (level) {

        qemu_system_reset_request();

    }

}



/* Board init.  */

static stellaris_board_info stellaris_boards[] = {

  { "LM3S811EVB",
@@ -1210,8 +1219,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
        0x40024000, 0x40025000, 0x40026000};

    static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};



    qemu_irq *pic;

    DeviceState *gpio_dev[7];

    DeviceState *gpio_dev[7], *nvic;

    qemu_irq gpio_in[7][8];

    qemu_irq gpio_out[7][8];

    qemu_irq adc;
@@ -1241,12 +1249,19 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
    vmstate_register_ram_global(sram);

    memory_region_add_subregion(system_memory, 0x20000000, sram);



    pic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,

    nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,

                      kernel_filename, cpu_model);



    qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,

                                qemu_allocate_irq(&do_sys_reset, NULL, 0));



    if (board->dc1 & (1 << 16)) {

        dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,

                                    pic[14], pic[15], pic[16], pic[17], NULL);

                                    qdev_get_gpio_in(nvic, 14),

                                    qdev_get_gpio_in(nvic, 15),

                                    qdev_get_gpio_in(nvic, 16),

                                    qdev_get_gpio_in(nvic, 17),

                                    NULL);

        adc = qdev_get_gpio_in(dev, 0);

    } else {

        adc = NULL;
@@ -1255,19 +1270,21 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
        if (board->dc2 & (0x10000 << i)) {

            dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,

                                       0x40030000 + i * 0x1000,

                                       pic[timer_irq[i]]);

                                       qdev_get_gpio_in(nvic, timer_irq[i]));

            /* TODO: This is incorrect, but we get away with it because

               the ADC output is only ever pulsed.  */

            qdev_connect_gpio_out(dev, 0, adc);

        }

    }



    stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);

    stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),

                       board, nd_table[0].macaddr.a);



    for (i = 0; i < 7; i++) {

        if (board->dc4 & (1 << i)) {

            gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],

                                               pic[gpio_irq[i]]);

                                               qdev_get_gpio_in(nvic,

                                                                gpio_irq[i]));

            for (j = 0; j < 8; j++) {

                gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);

                gpio_out[i][j] = NULL;
@@ -1276,7 +1293,8 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
    }



    if (board->dc2 & (1 << 12)) {

        dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);

        dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,

                                   qdev_get_gpio_in(nvic, 8));

        i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");

        if (board->peripherals & BP_OLED_I2C) {

            i2c_create_slave(i2c, "ssd0303", 0x3d);
@@ -1286,11 +1304,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
    for (i = 0; i < 4; i++) {

        if (board->dc2 & (1 << i)) {

            sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,

                                 pic[uart_irq[i]]);

                                 qdev_get_gpio_in(nvic, uart_irq[i]));

        }

    }

    if (board->dc2 & (1 << 4)) {

        dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);

        dev = sysbus_create_simple("pl022", 0x40008000,

                                   qdev_get_gpio_in(nvic, 7));

        if (board->peripherals & BP_OLED_SSI) {

            void *bus;

            DeviceState *sddev;
@@ -1326,7 +1345,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
        qdev_set_nic_properties(enet, &nd_table[0]);

        qdev_init_nofail(enet);

        sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);

        sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]);

        sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));

    }

    if (board->peripherals & BP_GAMEPAD) {

        qemu_irq gpad_irq[5];

hw/arm/stm32f205_soc.c

+8 −7
Original line number Diff line number Diff line
@@ -59,9 +59,8 @@ static void stm32f205_soc_initfn(Object *obj) 
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

{

    STM32F205State *s = STM32F205_SOC(dev_soc);

    DeviceState *syscfgdev, *usartdev, *timerdev;

    DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;

    SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;

    qemu_irq *pic;

    Error *err = NULL;

    int i;
@@ -88,7 +87,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 
    vmstate_register_ram_global(sram);

    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);



    pic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,

    nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,

                       s->kernel_filename, s->cpu_model);



    /* System configuration controller */
@@ -100,7 +99,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 
    }

    syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);

    sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);

    sysbus_connect_irq(syscfgbusdev, 0, pic[71]);

    sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));



    /* Attach UART (uses USART registers) and USART controllers */

    for (i = 0; i < STM_NUM_USARTS; i++) {
@@ -112,7 +111,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 
        }

        usartbusdev = SYS_BUS_DEVICE(usartdev);

        sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);

        sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);

        sysbus_connect_irq(usartbusdev, 0,

                           qdev_get_gpio_in(nvic, usart_irq[i]));

    }



    /* Timer 2 to 5 */
@@ -126,7 +126,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) 
        }

        timerbusdev = SYS_BUS_DEVICE(timerdev);

        sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);

        sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);

        sysbus_connect_irq(timerbusdev, 0,

                           qdev_get_gpio_in(nvic, timer_irq[i]));

    }

}