Unverified Commit 79bcac25 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
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riscv: plic: Log guest errors 



Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.

Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 0feb4a71

hw/riscv/sifive_plic.c

+9 −3
Original line number Diff line number Diff line
@@ -263,7 +263,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) 
    }



err:

    error_report("plic: invalid register read: %08x", (uint32_t)addr);

    qemu_log_mask(LOG_GUEST_ERROR,

                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",

                  __func__, addr);

    return 0;

}
@@ -290,7 +292,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, 
    } else if (addr >= plic->pending_base && /* 1 bit per source */

               addr < plic->pending_base + (plic->num_sources >> 3))

    {

        error_report("plic: invalid pending write: %08x", (uint32_t)addr);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: invalid pending write: 0x%" HWADDR_PRIx "",

                      __func__, addr);

        return;

    } else if (addr >= plic->enable_base && /* 1 bit per source */

        addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
@@ -340,7 +344,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, 
    }



err:

    error_report("plic: invalid register write: %08x", (uint32_t)addr);

    qemu_log_mask(LOG_GUEST_ERROR,

                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",

                  __func__, addr);

}



static const MemoryRegionOps sifive_plic_ops = {