Commit 787a7e76 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Peter Maydell
Browse files

target/arm: Declare some M-profile functions publicly 



In the next commit we will split the M-profile functions from this
file. Some function will be called out of helper.c. Declare them in
the "internals.h" header.

Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190701132516.26392-22-philmd@redhat.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b59f479b

target/arm/helper.c

+2 −36
Original line number Diff line number Diff line
@@ -39,21 +39,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, 
                               hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

                               target_ulong *page_size_ptr,

                               ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);



/* Security attributes for an address, as returned by v8m_security_lookup. */

typedef struct V8M_SAttributes {

    bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */

    bool ns;

    bool nsc;

    uint8_t sregion;

    bool srvalid;

    uint8_t iregion;

    bool irvalid;

} V8M_SAttributes;



static void v8m_security_lookup(CPUARMState *env, uint32_t address,

                                MMUAccessType access_type, ARMMMUIdx mmu_idx,

                                V8M_SAttributes *sattrs);

#endif



static void switch_mode(CPUARMState *env, int mode);
@@ -7733,25 +7718,6 @@ void arm_log_exception(int idx) 
    }

}



/*

 * Return true if the v7M CPACR permits access to the FPU for the specified

 * security state and privilege level.

 */

static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)

{

    switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {

    case 0:

    case 2: /* UNPREDICTABLE: we treat like 0 */

        return false;

    case 1:

        return is_priv;

    case 3:

        return true;

    default:

        g_assert_not_reached();

    }

}



/*

 * What kind of stack write are we doing? This affects how exceptions

 * generated during the stacking are treated.
@@ -12117,7 +12083,7 @@ static bool v8m_is_sau_exempt(CPUARMState *env, 
        (address >= 0xe00ff000 && address <= 0xe00fffff);

}



static void v8m_security_lookup(CPUARMState *env, uint32_t address,

void v8m_security_lookup(CPUARMState *env, uint32_t address,

                                MMUAccessType access_type, ARMMMUIdx mmu_idx,

                                V8M_SAttributes *sattrs)

{
@@ -12224,7 +12190,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, 
    }

}



static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,

bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,

                              MMUAccessType access_type, ARMMMUIdx mmu_idx,

                              hwaddr *phys_ptr, MemTxAttrs *txattrs,

                              int *prot, bool *is_subpage,

target/arm/internals.h

+42 −0
Original line number Diff line number Diff line
@@ -892,6 +892,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env) 
    }

}



/**

 * v7m_cpacr_pass:

 * Return true if the v7M CPACR permits access to the FPU for the specified

 * security state and privilege level.

 */

static inline bool v7m_cpacr_pass(CPUARMState *env,

                                  bool is_secure, bool is_priv)

{

    switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {

    case 0:

    case 2: /* UNPREDICTABLE: we treat like 0 */

        return false;

    case 1:

        return is_priv;

    case 3:

        return true;

    default:

        g_assert_not_reached();

    }

}



/**

 * aarch32_mode_name(): Return name of the AArch32 CPU mode

 * @psr: Program Status Register indicating CPU mode
@@ -988,6 +1009,27 @@ static inline int exception_target_el(CPUARMState *env) 


#ifndef CONFIG_USER_ONLY



/* Security attributes for an address, as returned by v8m_security_lookup. */

typedef struct V8M_SAttributes {

    bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */

    bool ns;

    bool nsc;

    uint8_t sregion;

    bool srvalid;

    uint8_t iregion;

    bool irvalid;

} V8M_SAttributes;



void v8m_security_lookup(CPUARMState *env, uint32_t address,

                         MMUAccessType access_type, ARMMMUIdx mmu_idx,

                         V8M_SAttributes *sattrs);



bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,

                       MMUAccessType access_type, ARMMMUIdx mmu_idx,

                       hwaddr *phys_ptr, MemTxAttrs *txattrs,

                       int *prot, bool *is_subpage,

                       ARMMMUFaultInfo *fi, uint32_t *mregion);



/* Cacheability and shareability attributes for a memory access */

typedef struct ARMCacheAttrs {

    unsigned int attrs:8; /* as in the MAIR register encoding */