Commit 7871abb9 authored Nov 17, 2015 by James Hogan Committed by Leon Alrae Nov 24, 2015

target-mips: Fix exceptions while UX=0



Commit 01f72885 ("target-mips: Status.UX/SX/KX enable 32-bit address
wrapping") added a new hflag MIPS_HFLAG_AWRAP, which indicates that
64-bit addressing is disallowed in the current mode, so hflag users
don't need to worry about the complexities of working that out, for
example checking both MIPS_HFLAG_KSU and MIPS_HFLAG_UX.

However when exceptions are taken outside of exception level,
mips_cpu_do_interrupt() manipulates the env->hflags directly rather than
using compute_hflags() to update them, and this code wasn't updated
accordingly. As a result, when UX is cleared, MIPS_HFLAG_AWRAP is set,
but it doesn't get cleared on entry back into kernel mode due to an
exception. Kernel mode then cannot access the 64-bit segments resulting
in a nested exception loop. The same applies to errors and debug
exceptions.

Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
flag when necessary, according to compute_hflags().

Fixes: 01f72885 ("target-mips: Status.UX/SX/KX enable 32-bit...")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

parent 5522a841

target-mips/helper.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -524,6 +524,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
		enter_debug_mode:
		if (env->insn_flags & ISA_MIPS3) {
		env->hflags \|= MIPS_HFLAG_64;
		if (!(env->insn_flags & ISA_MIPS64R6) \|\|
		env->CP0_Status & (1 << CP0St_KX)) {
		env->hflags &= ~MIPS_HFLAG_AWRAP;
		}
		}
		env->hflags \|= MIPS_HFLAG_DM \| MIPS_HFLAG_CP0;
		env->hflags &= ~(MIPS_HFLAG_KSU);
		@@ -548,6 +552,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
		env->CP0_Status \|= (1 << CP0St_ERL) \| (1 << CP0St_BEV);
		if (env->insn_flags & ISA_MIPS3) {
		env->hflags \|= MIPS_HFLAG_64;
		if (!(env->insn_flags & ISA_MIPS64R6) \|\|
		env->CP0_Status & (1 << CP0St_KX)) {
		env->hflags &= ~MIPS_HFLAG_AWRAP;
		}
		}
		env->hflags \|= MIPS_HFLAG_CP0;
		env->hflags &= ~(MIPS_HFLAG_KSU);
		@@ -725,6 +733,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
		env->CP0_Status \|= (1 << CP0St_EXL);
		if (env->insn_flags & ISA_MIPS3) {
		env->hflags \|= MIPS_HFLAG_64;
		if (!(env->insn_flags & ISA_MIPS64R6) \|\|
		env->CP0_Status & (1 << CP0St_KX)) {
		env->hflags &= ~MIPS_HFLAG_AWRAP;
		}
		}
		env->hflags \|= MIPS_HFLAG_CP0;
		env->hflags &= ~(MIPS_HFLAG_KSU);