Commit 78241762 authored by Nikunj A Dadhania's avatar Nikunj A Dadhania Committed by David Gibson
Browse files

target-ppc: Add xststdc[sp, dp, qp] instructions 



xststdcsp: VSX Scalar Test Data Class Single-Precision
xststdcdp: VSX Scalar Test Data Class Double-Precision
xststdcqp: VSX Scalar Test Data Class Quad-Precision

Signed-off-by: default avatarNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 403a884a

target/ppc/fpu_helper.c

+58 −8
Original line number Diff line number Diff line
@@ -3196,17 +3196,22 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode) 
 *   fld   - vsr_t field (VsrD(*) or VsrW(*))

 *   tfld   - target vsr_t field (VsrD(*) or VsrW(*))

 *   fld_max - target field max

 *   scrf - set result in CR and FPCC

 */

#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max)  \

#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf)  \

void helper_##op(CPUPPCState *env, uint32_t opcode)         \

{                                                           \

    ppc_vsr_t xt, xb;                                       \

    uint32_t i, sign, dcmx;                                 \

    uint32_t match = 0;                                     \

    uint32_t cc, match = 0;                                 \

                                                            \

    getVSR(xbn, &xb, env);                                  \

    if (!scrf) {                                            \

        memset(&xt, 0, sizeof(xt));                         \

        dcmx = DCMX_XV(opcode);                             \

    } else {                                                \

        dcmx = DCMX(opcode);                                \

    }                                                       \

                                                            \

    for (i = 0; i < nels; i++) {                            \

        sign = tp##_is_neg(xb.fld);                         \
@@ -3219,11 +3224,56 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ 
        } else if (tp##_is_zero_or_denormal(xb.fld)) {      \

            match = extract32(dcmx, 0 + !sign, 1);          \

        }                                                   \

                                                            \

        if (scrf) {                                         \

            cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT;  \

            env->fpscr &= ~(0x0F << FPSCR_FPRF);            \

            env->fpscr |= cc << FPSCR_FPRF;                 \

            env->crf[BF(opcode)] = cc;                      \

        } else {                                            \

            xt.tfld = match ? fld_max : 0;                  \

        }                                                   \

        match = 0;                                          \

    }                                                       \

    if (!scrf) {                                            \

        putVSR(xT(opcode), &xt, env);                       \

    }                                                       \

}



VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX)

VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX)
 
VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)

VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)

VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)

VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)



void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)

{

    ppc_vsr_t xb;

    uint32_t dcmx, sign, exp;

    uint32_t cc, match = 0, not_sp = 0;



    getVSR(xB(opcode), &xb, env);

    dcmx = DCMX(opcode);

    exp = (xb.VsrD(0) >> 52) & 0x7FF;



    sign = float64_is_neg(xb.VsrD(0));

    if (float64_is_any_nan(xb.VsrD(0))) {

        match = extract32(dcmx, 6, 1);

    } else if (float64_is_infinity(xb.VsrD(0))) {

        match = extract32(dcmx, 4 + !sign, 1);

    } else if (float64_is_zero(xb.VsrD(0))) {

        match = extract32(dcmx, 2 + !sign, 1);

    } else if (float64_is_zero_or_denormal(xb.VsrD(0)) ||

               (exp > 0 && exp < 0x381)) {

        match = extract32(dcmx, 0 + !sign, 1);

    }



    not_sp = !float64_eq(xb.VsrD(0),

                         float32_to_float64(

                             float64_to_float32(xb.VsrD(0), &env->fp_status),

                             &env->fp_status), &env->fp_status);



    cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;

    env->fpscr &= ~(0x0F << FPSCR_FPRF);

    env->fpscr |= cc << FPSCR_FPRF;

    env->crf[BF(opcode)] = cc;

}

target/ppc/helper.h

+3 −0
Original line number Diff line number Diff line
@@ -451,6 +451,9 @@ DEF_HELPER_2(xscvuxdsp, void, env, i32) 
DEF_HELPER_2(xscvsxdsp, void, env, i32)

DEF_HELPER_2(xscvudqp, void, env, i32)

DEF_HELPER_2(xscvuxddp, void, env, i32)

DEF_HELPER_2(xststdcsp, void, env, i32)

DEF_HELPER_2(xststdcdp, void, env, i32)

DEF_HELPER_2(xststdcqp, void, env, i32)

DEF_HELPER_2(xsrdpi, void, env, i32)

DEF_HELPER_2(xsrdpic, void, env, i32)

DEF_HELPER_2(xsrdpim, void, env, i32)

target/ppc/internal.h

+1 −0
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2); 
EXTRACT_HELPER(SHW, 8, 2);

EXTRACT_HELPER(SP, 19, 2);

EXTRACT_HELPER(IMM8, 11, 8);

EXTRACT_HELPER(DCMX, 16, 7);

EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);



typedef union _ppc_vsr_t {

target/ppc/translate/vsx-impl.inc.c

+3 −0
Original line number Diff line number Diff line
@@ -850,6 +850,9 @@ GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) 
GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)

GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)

GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)

GEN_VSX_HELPER_2(xststdcsp, 0x14, 0x12, 0, PPC2_ISA300)

GEN_VSX_HELPER_2(xststdcdp, 0x14, 0x16, 0, PPC2_ISA300)

GEN_VSX_HELPER_2(xststdcqp, 0x04, 0x16, 0, PPC2_ISA300)



GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)

GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)

target/ppc/translate/vsx-ops.inc.c

+4 −0
Original line number Diff line number Diff line
@@ -126,6 +126,10 @@ GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300), 
GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),

#endif



GEN_XX2FORM(xststdcdp, 0x14, 0x16, PPC2_ISA300),

GEN_XX2FORM(xststdcsp, 0x14, 0x12, PPC2_ISA300),

GEN_VSX_XFORM_300(xststdcqp, 0x04, 0x16, 0x00000001),



GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),

GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),

GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),