Commit 77596541 authored by Fredrik Noring's avatar Fredrik Noring Committed by Aleksandar Markovic
Browse files

target/mips: Define R5900 MMI1 opcode constants 



Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarFredrik Noring <noring@nocrew.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 3ef65697

target/mips/translate.c

+44 −0
Original line number Diff line number Diff line
@@ -2231,6 +2231,50 @@ enum { 
    TX79_MMI0_PPAC5  = (0x1F << 6) | TX79_MMI_CLASS_MMI0,

};









/*









 * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI1:









 *









 *  31    26                        10     6 5      0









 * +--------+----------------------+--------+--------+









 * |   MMI  |                      |function|  MMI1  |









 * +--------+----------------------+--------+--------+









 *









 * function  bits 7..6









 *     bits |   0   |   1   |   2   |   3









 *    10..8 |   00  |   01  |   10  |   11









 *   -------+-------+-------+-------+-------









 *    0 000 |   *   | PABSW | PCEQW | PMINW









 *    1 001 | PADSBH| PABSH | PCEQH | PMINH









 *    2 010 |   *   |   *   | PCEQB |   *









 *    3 011 |   *   |   *   |   *   |   *









 *    4 100 | PADDUW| PSUBUW| PEXTUW|   *









 *    5 101 | PADDUH| PSUBUH| PEXTUH|   *









 *    6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV









 *    7 111 |   *   |   *   |   *   |   *









 */

















#define MASK_TX79_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))









enum {









    TX79_MMI1_PABSW  = (0x01 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PCEQW  = (0x02 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PMINW  = (0x03 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PADSBH = (0x04 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PABSH  = (0x05 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PCEQH  = (0x06 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PMINH  = (0x07 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PCEQB  = (0x0A << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PADDUW = (0x10 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PSUBUW = (0x11 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PEXTUW = (0x12 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PADDUH = (0x14 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PSUBUH = (0x15 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PEXTUH = (0x16 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PADDUB = (0x18 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PSUBUB = (0x19 << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_PEXTUB = (0x1A << 6) | TX79_MMI_CLASS_MMI1,









    TX79_MMI1_QFSRV  = (0x1B << 6) | TX79_MMI_CLASS_MMI1,









};

















/* global register indices */









static TCGv cpu_gpr[32], cpu_PC;









static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];