Commit 7721a304 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging 



----------------------------------------------------------------
target-arm queue:
 * support -bios option in vexpress boards
 * register the Cortex-A57 impdef system registers
 * fix handling of UXN bit in ARMv8 page tables
 * complete support of crypto insns in A32/T32
 * implement CRC and crypto insns in A64
 * fix bugs in generic timer control register

----------------------------------------------------------------

# gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140609-1:
  target-arm: Delete unused iwmmxt_msadb helper
  target-arm: Fix errors in writes to generic timer control registers
  target-arm: A64: Implement two-register SHA instructions
  target-arm: A64: Implement 3-register SHA instructions
  target-arm: A64: Implement AES instructions
  target-arm: A32/T32: Mask CRC value in calling code, not helper
  target-arm: A64: Implement CRC instructions
  target-arm: VFPv4 implies half-precision extension
  target-arm: Clean up handling of ARMv8 optional feature bits
  target-arm: Remove unnecessary setting of feature bits
  target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
  target-arm: A64: Use PMULL feature bit for PMULL
  target-arm: add support for v8 VMULL.P64 instruction
  target-arm: Allow 3reg_wide undefreq to encode more bad size options
  target-arm: add support for v8 SHA1 and SHA256 instructions
  target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
  target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
  target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
  vexpress: Add support for the -bios flag to provide firmware

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 14ac5733 3b1a4138

hw/arm/vexpress.c

+13 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "net/net.h"

#include "sysemu/sysemu.h"

#include "hw/boards.h"

#include "hw/loader.h"

#include "exec/address-spaces.h"

#include "sysemu/blockdev.h"

#include "hw/block/flash.h"
@@ -528,6 +529,18 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, 
    daughterboard->init(daughterboard, machine->ram_size, machine->cpu_model,

                        pic);



    /*

     * If a bios file was provided, attempt to map it into memory

     */

    if (bios_name) {

        const char *fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);

        if (!fn || load_image_targphys(fn, map[VE_NORFLASH0],

                                       VEXPRESS_FLASH_SIZE) < 0) {

            error_report("Could not load ROM image '%s'", bios_name);

            exit(1);

        }

    }



    /* Motherboard peripherals: the wiring is the same but the

     * addresses vary between the legacy and A-Series memory maps.

     */

linux-user/elfload.c

+8 −1
Original line number Diff line number Diff line
@@ -468,6 +468,9 @@ static uint32_t get_elf_hwcap2(void) 
    uint32_t hwcaps = 0;



    GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP2_ARM_AES);

    GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP2_ARM_PMULL);

    GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP2_ARM_SHA1);

    GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP2_ARM_SHA2);

    GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP2_ARM_CRC32);

    return hwcaps;

}
@@ -536,7 +539,11 @@ static uint32_t get_elf_hwcap(void) 
    /* probe for the extra features */

#define GET_FEATURE(feat, hwcap) \

    do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)

    GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_PMULL);

    GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES);

    GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);

    GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1);

    GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2);

    GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);

#undef GET_FEATURE



    return hwcaps;

target-arm/cpu.c

+5 −8
Original line number Diff line number Diff line
@@ -316,7 +316,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
        set_feature(env, ARM_FEATURE_V7);

        set_feature(env, ARM_FEATURE_ARM_DIV);

        set_feature(env, ARM_FEATURE_LPAE);

        set_feature(env, ARM_FEATURE_V8_AES);

    }

    if (arm_feature(env, ARM_FEATURE_V7)) {

        set_feature(env, ARM_FEATURE_VAPA);
@@ -349,6 +348,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
    }

    if (arm_feature(env, ARM_FEATURE_VFP4)) {

        set_feature(env, ARM_FEATURE_VFP3);

        set_feature(env, ARM_FEATURE_VFP_FP16);

    }

    if (arm_feature(env, ARM_FEATURE_VFP3)) {

        set_feature(env, ARM_FEATURE_VFP);
@@ -745,7 +745,6 @@ static void cortex_a15_initfn(Object *obj) 
    cpu->dtb_compatible = "arm,cortex-a15";

    set_feature(&cpu->env, ARM_FEATURE_V7);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);

    set_feature(&cpu->env, ARM_FEATURE_NEON);

    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);

    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
@@ -954,15 +953,13 @@ static void arm_any_initfn(Object *obj) 
    ARMCPU *cpu = ARM_CPU(obj);

    set_feature(&cpu->env, ARM_FEATURE_V8);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);

    set_feature(&cpu->env, ARM_FEATURE_NEON);

    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);

    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);

    set_feature(&cpu->env, ARM_FEATURE_V7MP);

    set_feature(&cpu->env, ARM_FEATURE_V8_AES);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

    set_feature(&cpu->env, ARM_FEATURE_CRC);

#ifdef TARGET_AARCH64

    set_feature(&cpu->env, ARM_FEATURE_AARCH64);

#endif

    cpu->midr = 0xffffffff;

}

#endif

target-arm/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -635,6 +635,9 @@ enum arm_features { 
    ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */

    ARM_FEATURE_EL2, /* has EL2 Virtualization support */

    ARM_FEATURE_EL3, /* has EL3 Secure monitor support */

    ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */

    ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */

    ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */

};



static inline int arm_feature(CPUARMState *env, int feature)

target-arm/cpu64.c

+11 −4
Original line number Diff line number Diff line
@@ -93,11 +93,15 @@ static void aarch64_a57_initfn(Object *obj) 


    set_feature(&cpu->env, ARM_FEATURE_V8);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);

    set_feature(&cpu->env, ARM_FEATURE_NEON);

    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);

    set_feature(&cpu->env, ARM_FEATURE_AARCH64);

    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);

    set_feature(&cpu->env, ARM_FEATURE_V8_AES);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

    set_feature(&cpu->env, ARM_FEATURE_CRC);

    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;

    cpu->midr = 0x411fd070;

    cpu->reset_fpsid = 0x41034070;
@@ -128,6 +132,7 @@ static void aarch64_a57_initfn(Object *obj) 
    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */

    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */

    cpu->dcz_blocksize = 4; /* 64 bytes */

    define_arm_cp_regs(cpu, cortexa57_cp_reginfo);

}



#ifdef CONFIG_USER_ONLY
@@ -137,11 +142,13 @@ static void aarch64_any_initfn(Object *obj) 


    set_feature(&cpu->env, ARM_FEATURE_V8);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);

    set_feature(&cpu->env, ARM_FEATURE_NEON);

    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);

    set_feature(&cpu->env, ARM_FEATURE_V7MP);

    set_feature(&cpu->env, ARM_FEATURE_AARCH64);

    set_feature(&cpu->env, ARM_FEATURE_V8_AES);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);

    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);

    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);

    set_feature(&cpu->env, ARM_FEATURE_CRC);

    cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */

    cpu->dcz_blocksize = 7; /*  512 bytes */

}