Commit 76b7dd64 authored by Max Filippov's avatar Max Filippov
Browse files

target/xtensa: convert to do_transaction_failed 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 9a124b69

target/xtensa/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 
#else

    cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;

    cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;

    cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;

    cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;

#endif

    cc->debug_excp_handler = xtensa_breakpoint_handler;

    cc->disas_set_info = xtensa_cpu_disas_set_info;

target/xtensa/cpu.h

+4 −3
Original line number Diff line number Diff line
@@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, 
                                int mmu_idx);

void xtensa_cpu_do_interrupt(CPUState *cpu);

bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);

void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,

                                     bool is_write, bool is_exec, int opaque,

                                     unsigned size);

void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,

                                      unsigned size, MMUAccessType access_type,

                                      int mmu_idx, MemTxAttrs attrs,

                                      MemTxResult response, uintptr_t retaddr);

void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,

                           fprintf_function cpu_fprintf, int flags);

hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

target/xtensa/helper.c

+23 −7
Original line number Diff line number Diff line
@@ -566,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_write) 
    }

}



static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);

static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);



static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,

        uint32_t vaddr, int is_write, int mmu_idx,
@@ -584,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, 
    int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);



    if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&

            may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {

            may_lookup_pt && get_pte(env, vaddr, &pte)) {

        ring = (pte >> 4) & 0x3;

        wi = 0;

        split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
@@ -631,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, 
    return 0;

}



static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)

static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)

{

    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    uint32_t paddr;
@@ -642,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) 
    int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,

            &paddr, &page_size, &access, false);



    qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",

                  __func__, vaddr, ret ? ~0 : paddr);

    if (ret == 0) {

        qemu_log_mask(CPU_LOG_MMU,

                      "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",

                      __func__, vaddr, pt_vaddr, paddr);

    } else {

        qemu_log_mask(CPU_LOG_MMU,

                      "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",

                      __func__, vaddr, pt_vaddr, ret);

    }



    if (ret == 0) {

        *pte = ldl_phys(cs->as, paddr);

        MemTxResult result;



        *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,

                                 &result);

        if (result != MEMTX_OK) {

            qemu_log_mask(CPU_LOG_MMU,

                          "%s: couldn't load PTE: transaction failed (%u)\n",

                          __func__, (unsigned)result);

            ret = 1;

        }

    return ret;

    }

    return ret == 0;

}



static int get_physical_addr_region(CPUXtensaState *env,

target/xtensa/op_helper.c

+7 −5
Original line number Diff line number Diff line
@@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size, 
    }

}



void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,

                                     bool is_write, bool is_exec, int opaque,

                                     unsigned size)

void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,

                                      unsigned size, MMUAccessType access_type,

                                      int mmu_idx, MemTxAttrs attrs,

                                      MemTxResult response, uintptr_t retaddr)

{

    XtensaCPU *cpu = XTENSA_CPU(cs);

    CPUXtensaState *env = &cpu->env;



    cpu_restore_state(cs, retaddr, true);

    HELPER(exception_cause_vaddr)(env, env->pc,

                                  is_exec ?

                                  access_type == MMU_INST_FETCH ?

                                  INSTR_PIF_ADDR_ERROR_CAUSE :

                                  LOAD_STORE_PIF_ADDR_ERROR_CAUSE,

                                  is_exec ? addr : cs->mem_io_vaddr);

                                  addr);

}



static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)