Commit 7692401a authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150715' into staging 



target arm queue:
 * handle broken AArch64 kernels which assume DTB won't cross a 2MB boundary
 * correct broken SCTLR_EL3 reset value

# gpg: Signature made Wed Jul 15 17:24:24 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150715:
  hw/arm/boot: Increase fdt alignment
  target-arm: Fix broken SCTLR_EL3 reset

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 711dc6f3 76e2aef3

hw/arm/boot.c

+22 −6
Original line number Diff line number Diff line
@@ -735,12 +735,28 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) 
         * we point to the kernel args.

         */

        if (have_dtb(info)) {

            /* Place the DTB after the initrd in memory. Note that some

             * kernels will trash anything in the 4K page the initrd

             * ends in, so make sure the DTB isn't caught up in that.

            hwaddr align;

            hwaddr dtb_start;



            if (elf_machine == EM_AARCH64) {

                /*

                 * Some AArch64 kernels on early bootup map the fdt region as

                 *

                 *   [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]

                 *

                 * Let's play safe and prealign it to 2MB to give us some space.

                 */

            hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,

                                             4096);

                align = 2 * 1024 * 1024;

            } else {

                /*

                 * Some 32bit kernels will trash anything in the 4K page the

                 * initrd ends in, so make sure the DTB isn't caught up in that.

                 */

                align = 4096;

            }



            /* Place the DTB after the initrd in memory with alignment. */

            dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align);

            if (load_dtb(dtb_start, info, 0) < 0) {

                exit(1);

            }

target-arm/helper.c

+1 −0
Original line number Diff line number Diff line
@@ -2752,6 +2752,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,

      .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },

    { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */

      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,

      .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },