Commit 76462405 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160606-1' into staging 



target-arm queue:
 * support instruction syndrome info for data aborts from A64 to EL2
 * add HSTR_EL2 register
 * fix incorrect ESR IL bits in various syndrome register cases
 * virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range
 * gicv2: RAZ/WI non-sec access to sec interrupts
 * i2c: add aspeed i2c controller
 * virt: Reject gic-version=host for non-KVM (don't segv on aarch64 host)
 * xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
 * xlnx-zynqmp: Support KVM on AArch64 hosts
 * ptimer: Various fixes for awkward corner cases
 * char: QOMify various ARM UART models
 * char: get rid of qemu_char_get_next_serial
 * target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
 * zynqmp: Add the ZCU102 board

# gpg: Signature made Mon 06 Jun 2016 17:01:11 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20160606-1: (25 commits)
  zynqmp: Add the ZCU102 board
  target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
  char: get rid of qemu_char_get_next_serial
  hw/char: QOM'ify xilinx_uartlite model
  hw/char: QOM'ify stm32f2xx_usart model
  hw/char: QOM'ify digic-uart model
  hw/char: QOM'ify cadence_uart model
  hw/char: QOM'ify pl011 model
  hw/ptimer: Introduce ptimer_get_limit
  hw/ptimer: Support "on the fly" timer mode switch
  hw/ptimer: Update .delta on period/freq change
  hw/ptimer: Perform counter wrap around if timer already expired
  hw/ptimer: Fix issues caused by the adjusted timer limit value
  xlnx-zynqmp: Use the in kernel GIC model for KVM runs
  xlnx-zynqmp: Delay realization of GIC until post CPU realization
  xlnx-zynqmp: Make the RPU subsystem optional
  xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
  hw/arm/virt: Reject gic-version=host for non-KVM
  i2c: add aspeed i2c controller
  hw/intc/gic: RAZ/WI non-sec access to sec interrupts
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 280b2358 0c18c6c6

hw/arm/ast2400.c

+16 −0
Original line number Diff line number Diff line
@@ -18,12 +18,14 @@ 
#include "hw/arm/ast2400.h"

#include "hw/char/serial.h"

#include "qemu/log.h"

#include "hw/i2c/aspeed_i2c.h"



#define AST2400_UART_5_BASE      0x00184000

#define AST2400_IOMEM_SIZE       0x00200000

#define AST2400_IOMEM_BASE       0x1E600000

#define AST2400_VIC_BASE         0x1E6C0000

#define AST2400_TIMER_BASE       0x1E782000

#define AST2400_I2C_BASE         0x1E78A000



static const int uart_irqs[] = { 9, 32, 33, 34, 10 };

static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@@ -66,6 +68,10 @@ static void ast2400_init(Object *obj) 
    object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);

    object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);

    qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());



    object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);

    object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);

    qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());

}



static void ast2400_realize(DeviceState *dev, Error **errp)
@@ -110,6 +116,16 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,

                       uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);

    }



    /* I2C */

    object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,

                       qdev_get_gpio_in(DEVICE(&s->vic), 12));

}



static void ast2400_class_init(ObjectClass *oc, void *data)

hw/arm/bcm2835_peripherals.c

+3 −13
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "hw/misc/bcm2835_mbox_defs.h"

#include "hw/arm/raspi_platform.h"

#include "sysemu/char.h"

#include "sysemu/sysemu.h"



/* Peripheral base address on the VC (GPU) system bus */

#define BCM2835_VC_PERI_BASE 0x7e000000
@@ -106,7 +107,6 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    MemoryRegion *ram;

    Error *err = NULL;

    uint32_t ram_size, vcram_size;

    CharDriverState *chr;

    int n;



    obj = object_property_get_link(OBJECT(dev), "ram", &err);
@@ -147,6 +147,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));



    /* UART0 */

    qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hds[0]);

    object_property_set_bool(OBJECT(s->uart0), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);
@@ -158,17 +159,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    sysbus_connect_irq(s->uart0, 0,

        qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,

                               INTERRUPT_UART));



    /* AUX / UART1 */

    /* TODO: don't call qemu_char_get_next_serial() here, instead set

     * chardev properties for each uart at the board level, once pl011

     * (uart0) has been updated to avoid qemu_char_get_next_serial()

     */

    chr = qemu_char_get_next_serial();

    if (chr == NULL) {

        chr = qemu_chr_new("bcm2835.uart1", "null", NULL);

    }

    qdev_prop_set_chr(DEVICE(&s->aux), "chardev", chr);

    qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hds[1]);



    object_property_set_bool(OBJECT(&s->aux), true, "realized", &err);

    if (err) {
@@ -292,8 +284,6 @@ static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) 
    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = bcm2835_peripherals_realize;

    /* Reason: realize() method uses qemu_char_get_next_serial() */

    dc->cannot_instantiate_with_device_add_yet = true;

}



static const TypeInfo bcm2835_peripherals_type_info = {

hw/arm/digic.c

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "qemu/osdep.h"

#include "qapi/error.h"

#include "hw/arm/digic.h"

#include "sysemu/sysemu.h"



#define DIGIC4_TIMER_BASE(n)    (0xc0210000 + (n) * 0x100)
@@ -84,6 +85,7 @@ static void digic_realize(DeviceState *dev, Error **errp) 
        sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));

    }



    qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hds[0]);

    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);

    if (err != NULL) {

        error_propagate(errp, err);

hw/arm/highbank.c

+2 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include "sysemu/block-backend.h"

#include "exec/address-spaces.h"

#include "qemu/error-report.h"

#include "hw/char/pl011.h"



#define SMP_BOOT_ADDR           0x100

#define SMP_BOOT_REG            0x40
@@ -326,7 +327,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 
    busdev = SYS_BUS_DEVICE(dev);

    sysbus_mmio_map(busdev, 0, 0xfff34000);

    sysbus_connect_irq(busdev, 0, pic[18]);

    sysbus_create_simple("pl011", 0xfff36000, pic[20]);

    pl011_create(0xfff36000, pic[20], serial_hds[0]);



    dev = qdev_create(NULL, "highbank-regs");

    qdev_init_nofail(dev);

hw/arm/integratorcp.c

+3 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"

#include "qemu/error-report.h"

#include "hw/char/pl011.h"



#define TYPE_INTEGRATOR_CM "integrator_core"

#define INTEGRATOR_CM(obj) \
@@ -588,8 +589,8 @@ static void integratorcp_init(MachineState *machine) 
    sysbus_create_varargs("integrator_pit", 0x13000000,

                          pic[5], pic[6], pic[7], NULL);

    sysbus_create_simple("pl031", 0x15000000, pic[8]);

    sysbus_create_simple("pl011", 0x16000000, pic[1]);

    sysbus_create_simple("pl011", 0x17000000, pic[2]);

    pl011_create(0x16000000, pic[1], serial_hds[0]);

    pl011_create(0x17000000, pic[2], serial_hds[1]);

    icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,

                               qdev_get_gpio_in(sic, 3));

    sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);