Commit 750541c4 authored by Aleksandar Markovic's avatar Aleksandar Markovic
Browse files

target/mips: Amend and cleanup MSA TCG tests 



Add missing bits and peaces of the tests of the emulation of certain
MSA (non-immediate variants): some tests were missing two last cases;
some instructions were missing wrappers; some test included wrong
headers; some tests were missing altogether; updated some copywright
preambles; do several other minor cleanups.

Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarMateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: default avatarAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1555699081-24577-4-git-send-email-aleksandar.markovic@rt-rk.com>
parent fd487f83

tests/tcg/mips/include/test_utils_128.h

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ static inline int32_t check_results(const char *instruction_name, 
        }

    }



    printf("PASS: %3d   FAIL: %3d   elapsed time: %5.2f ms\n",

    printf("\tPASS: %3d \tFAIL: %3d \telapsed time: %5.2f ms\n",

           pass_count, fail_count, elapsed_time);



    if (fail_count > 0) {

tests/tcg/mips/include/wrappers_msa.h

+143 −4
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ 




#define DO_MSA__WD__WS(suffix, mnemonic)                               \

static inline void do_msa_##suffix(void *input, void *output)          \

static inline void do_msa_##suffix(const void *input,                  \

                                   const void *output)                 \

{                                                                      \

   __asm__ volatile (                                                  \

      "move $t0, %0\n\t"                                               \
@@ -39,7 +40,8 @@ static inline void do_msa_##suffix(void *input, void *output) \ 
}



#define DO_MSA__WD__WD(suffix, mnemonic)                               \

static inline void do_msa_##suffix(void *input, void *output)          \

static inline void do_msa_##suffix(const void *input,                  \

                                   const void *output)                 \

{                                                                      \

   __asm__ volatile (                                                  \

      "move $t0, %0\n\t"                                               \
@@ -70,8 +72,9 @@ DO_MSA__WD__WS(PCNT_D, pcnt.d) 




#define DO_MSA__WD__WS_WT(suffix, mnemonic)                            \

static inline void do_msa_##suffix(void *input1, void *input2,         \

                                   void *output)                       \

static inline void do_msa_##suffix(const void *input1,                 \

                                   const void *input2,                 \

                                   const void *output)                 \

{                                                                      \

   __asm__ volatile (                                                  \

      "move $t0, %0\n\t"                                               \
@@ -258,6 +261,142 @@ DO_MSA__WD__WS_WT(SRLR_H, srlr.h) 
DO_MSA__WD__WS_WT(SRLR_W, srlr.w)

DO_MSA__WD__WS_WT(SRLR_D, srlr.d)



DO_MSA__WD__WS_WT(ADD_A_B, add_a.b)

DO_MSA__WD__WS_WT(ADD_A_H, add_a.h)

DO_MSA__WD__WS_WT(ADD_A_W, add_a.w)

DO_MSA__WD__WS_WT(ADD_A_D, add_a.d)



DO_MSA__WD__WS_WT(ADDS_A_B, adds_a.b)

DO_MSA__WD__WS_WT(ADDS_A_H, adds_a.h)

DO_MSA__WD__WS_WT(ADDS_A_W, adds_a.w)

DO_MSA__WD__WS_WT(ADDS_A_D, adds_a.d)



DO_MSA__WD__WS_WT(ADDS_S_B, adds_s.b)

DO_MSA__WD__WS_WT(ADDS_S_H, adds_s.h)

DO_MSA__WD__WS_WT(ADDS_S_W, adds_s.w)

DO_MSA__WD__WS_WT(ADDS_S_D, adds_s.d)



DO_MSA__WD__WS_WT(ADDS_U_B, adds_u.b)

DO_MSA__WD__WS_WT(ADDS_U_H, adds_u.h)

DO_MSA__WD__WS_WT(ADDS_U_W, adds_u.w)

DO_MSA__WD__WS_WT(ADDS_U_D, adds_u.d)



DO_MSA__WD__WS_WT(ADDV_B, addv.b)

DO_MSA__WD__WS_WT(ADDV_H, addv.h)

DO_MSA__WD__WS_WT(ADDV_W, addv.w)

DO_MSA__WD__WS_WT(ADDV_D, addv.d)



DO_MSA__WD__WS_WT(HADD_S_H, hadd_s.h)

DO_MSA__WD__WS_WT(HADD_S_W, hadd_s.w)

DO_MSA__WD__WS_WT(HADD_S_D, hadd_s.d)



DO_MSA__WD__WS_WT(HADD_U_H, hadd_u.h)

DO_MSA__WD__WS_WT(HADD_U_W, hadd_u.w)

DO_MSA__WD__WS_WT(HADD_U_D, hadd_u.d)



DO_MSA__WD__WS_WT(AVER_S_B, aver_s.b)

DO_MSA__WD__WS_WT(AVER_S_H, aver_s.h)

DO_MSA__WD__WS_WT(AVER_S_W, aver_s.w)

DO_MSA__WD__WS_WT(AVER_S_D, aver_s.d)



DO_MSA__WD__WS_WT(AVER_U_B, aver_u.b)

DO_MSA__WD__WS_WT(AVER_U_H, aver_u.h)

DO_MSA__WD__WS_WT(AVER_U_W, aver_u.w)

DO_MSA__WD__WS_WT(AVER_U_D, aver_u.d)



DO_MSA__WD__WS_WT(AVE_S_B, ave_s.b)

DO_MSA__WD__WS_WT(AVE_S_H, ave_s.h)

DO_MSA__WD__WS_WT(AVE_S_W, ave_s.w)

DO_MSA__WD__WS_WT(AVE_S_D, ave_s.d)



DO_MSA__WD__WS_WT(AVE_U_B, ave_u.b)

DO_MSA__WD__WS_WT(AVE_U_H, ave_u.h)

DO_MSA__WD__WS_WT(AVE_U_W, ave_u.w)

DO_MSA__WD__WS_WT(AVE_U_D, ave_u.d)



DO_MSA__WD__WS_WT(DIV_S_B, div_s.b)

DO_MSA__WD__WS_WT(DIV_S_H, div_s.h)

DO_MSA__WD__WS_WT(DIV_S_W, div_s.w)

DO_MSA__WD__WS_WT(DIV_S_D, div_s.d)



DO_MSA__WD__WS_WT(DIV_U_B, div_u.b)

DO_MSA__WD__WS_WT(DIV_U_H, div_u.h)

DO_MSA__WD__WS_WT(DIV_U_W, div_u.w)

DO_MSA__WD__WS_WT(DIV_U_D, div_u.d)



DO_MSA__WD__WS_WT(DOTP_S_H, dotp_s.h)

DO_MSA__WD__WS_WT(DOTP_S_W, dotp_s.w)

DO_MSA__WD__WS_WT(DOTP_S_D, dotp_s.d)



DO_MSA__WD__WS_WT(DOTP_U_H, dotp_u.h)

DO_MSA__WD__WS_WT(DOTP_U_W, dotp_u.w)

DO_MSA__WD__WS_WT(DOTP_U_D, dotp_u.d)



DO_MSA__WD__WS_WT(MOD_S_B, mod_s.b)

DO_MSA__WD__WS_WT(MOD_S_H, mod_s.h)

DO_MSA__WD__WS_WT(MOD_S_W, mod_s.w)

DO_MSA__WD__WS_WT(MOD_S_D, mod_s.d)



DO_MSA__WD__WS_WT(MOD_U_B, mod_u.b)

DO_MSA__WD__WS_WT(MOD_U_H, mod_u.h)

DO_MSA__WD__WS_WT(MOD_U_W, mod_u.w)

DO_MSA__WD__WS_WT(MOD_U_D, mod_u.d)



DO_MSA__WD__WS_WT(MUL_Q_H, mul_q.h)

DO_MSA__WD__WS_WT(MUL_Q_W, mul_q.w)

DO_MSA__WD__WS_WT(MULR_Q_H, mulr_q.h)

DO_MSA__WD__WS_WT(MULR_Q_W, mulr_q.w)



DO_MSA__WD__WS_WT(MULV_B, mulv.b)

DO_MSA__WD__WS_WT(MULV_H, mulv.h)

DO_MSA__WD__WS_WT(MULV_W, mulv.w)

DO_MSA__WD__WS_WT(MULV_D, mulv.d)



DO_MSA__WD__WS_WT(SUBV_B, subv.b)

DO_MSA__WD__WS_WT(SUBV_H, subv.h)

DO_MSA__WD__WS_WT(SUBV_W, subv.w)

DO_MSA__WD__WS_WT(SUBV_D, subv.d)



DO_MSA__WD__WS_WT(SUBS_S_B, subs_s.b)

DO_MSA__WD__WS_WT(SUBS_S_H, subs_s.h)

DO_MSA__WD__WS_WT(SUBS_S_W, subs_s.w)

DO_MSA__WD__WS_WT(SUBS_S_D, subs_s.d)



DO_MSA__WD__WS_WT(SUBS_U_B, subs_u.b)

DO_MSA__WD__WS_WT(SUBS_U_H, subs_u.h)

DO_MSA__WD__WS_WT(SUBS_U_W, subs_u.w)

DO_MSA__WD__WS_WT(SUBS_U_D, subs_u.d)



DO_MSA__WD__WS_WT(ASUB_S_B, asub_s.b)

DO_MSA__WD__WS_WT(ASUB_S_H, asub_s.h)

DO_MSA__WD__WS_WT(ASUB_S_W, asub_s.w)

DO_MSA__WD__WS_WT(ASUB_S_D, asub_s.d)



DO_MSA__WD__WS_WT(ASUB_U_B, asub_u.b)

DO_MSA__WD__WS_WT(ASUB_U_H, asub_u.h)

DO_MSA__WD__WS_WT(ASUB_U_W, asub_u.w)

DO_MSA__WD__WS_WT(ASUB_U_D, asub_u.d)



DO_MSA__WD__WS_WT(SUBSUU_S_B, subsuu_s.b)

DO_MSA__WD__WS_WT(SUBSUU_S_H, subsuu_s.h)

DO_MSA__WD__WS_WT(SUBSUU_S_W, subsuu_s.w)

DO_MSA__WD__WS_WT(SUBSUU_S_D, subsuu_s.d)



DO_MSA__WD__WS_WT(SUBSUS_U_B, subsus_u.b)

DO_MSA__WD__WS_WT(SUBSUS_U_H, subsus_u.h)

DO_MSA__WD__WS_WT(SUBSUS_U_W, subsus_u.w)

DO_MSA__WD__WS_WT(SUBSUS_U_D, subsus_u.d)



DO_MSA__WD__WS_WT(HSUB_S_H, hsub_s.h)

DO_MSA__WD__WS_WT(HSUB_S_W, hsub_s.w)

DO_MSA__WD__WS_WT(HSUB_S_D, hsub_s.d)



DO_MSA__WD__WS_WT(HSUB_U_H, hsub_u.h)

DO_MSA__WD__WS_WT(HSUB_U_W, hsub_u.w)

DO_MSA__WD__WS_WT(HSUB_U_D, hsub_u.d)







DO_MSA__WD__WS_WT(BMNZ_V, bmnz.v)

DO_MSA__WD__WS_WT(BMZ_V, bmz.v)

tests/tcg/mips/user/ase/msa/int-add/test_msa_add_a_b.c

+4 −0
Original line number Diff line number Diff line 
/*

 *  Test program for MSA instruction ADD_A.B

 *

 *  Copyright (C) 2019  Wave Computing, Inc.

 *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>

 *  Copyright (C) 2019  RT-RK Computer Based Systems LLC

 *  Copyright (C) 2019  Mateja Marjanovic <mateja.marjanovic@rt-rk.com>

 *
@@ -119,6 +121,8 @@ int32_t main(void) 
        { 0xc4a968a3a56293ceULL, 0x9a37b229ac6d4374ULL, },

        { 0xe8b930818693738eULL, 0xbe76838659bd6e6cULL, },

        { 0x759116b0ab9e5756ULL, 0x8518bd426c817064ULL, },

        { 0xc4a968a3a56293ceULL, 0x9a37b229ac6d4374ULL, },

        { 0xe09e2c9abc623c9cULL, 0xe61ef050ae843cc0ULL, },

};



    gettimeofday(&start, NULL);

tests/tcg/mips/user/ase/msa/int-add/test_msa_add_a_d.c

+4 −0
Original line number Diff line number Diff line 
/*

 *  Test program for MSA instruction ADD_A.D

 *

 *  Copyright (C) 2019  Wave Computing, Inc.

 *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>

 *  Copyright (C) 2019  RT-RK Computer Based Systems LLC

 *  Copyright (C) 2019  Mateja Marjanovic <mateja.marjanovic@rt-rk.com>

 *
@@ -119,6 +121,8 @@ int32_t main(void) 
        { 0xc3f467a2a46256ceULL, 0x99e73e2701e84274ULL, },

        { 0xe7e42f8135cf8d0eULL, 0xbd7582865538cd6cULL, },

        { 0x749115ea109e1b46ULL, 0x850632416bfc705cULL, },

        { 0xc3f467a2a46256ceULL, 0x99e73e2701e84274ULL, },

        { 0xe09e2c9abc63c49cULL, 0xe41cee4ead7a3ac0ULL, },

};



    gettimeofday(&start, NULL);

tests/tcg/mips/user/ase/msa/int-add/test_msa_add_a_h.c

+4 −0
Original line number Diff line number Diff line 
/*

 *  Test program for MSA instruction ADD_A.H

 *

 *  Copyright (C) 2019  Wave Computing, Inc.

 *  Copyright (C) 2019  Aleksandar Markovic <amarkovic@wavecomp.com>

 *  Copyright (C) 2019  RT-RK Computer Based Systems LLC

 *  Copyright (C) 2019  Mateja Marjanovic <mateja.marjanovic@rt-rk.com>

 *
@@ -119,6 +121,8 @@ int32_t main(void) 
        { 0xc3f567a3a4629232ULL, 0x99e7b029ab934274ULL, },

        { 0xe7e52f81869372f2ULL, 0xbd76828658436d54ULL, },

        { 0x749116b0abc456aaULL, 0x8506bc0e6bfd705cULL, },

        { 0xc3f567a3a4629232ULL, 0x99e7b029ab934274ULL, },

        { 0xe09e2c9abc623b64ULL, 0xe41eee50ad7c3ac0ULL, },

};



    gettimeofday(&start, NULL);