Commit 73c69456 authored by Alistair Francis's avatar Alistair Francis Committed by Edgar E. Iglesias
Browse files

Microblaze: Convert Microblaze-pic handling to GPIOs 



This patch uses inbound GPIO lines (IRQ and FIR) for
interrupts instead of using the old pic_cpu method,
which doesn't correspond to real hardware.

This creates the CPU's inbound IRQ and FIR GPIO lines and
updates the Microblaze boards to use this new method.

Signed-off-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Suggested-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Reveiwed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 83e6813a

hw/microblaze/Makefile.objs

+0 −1
Original line number Diff line number Diff line 
obj-y += petalogix_s3adsp1800_mmu.o

obj-y += petalogix_ml605_mmu.o

obj-y += boot.o
 
obj-y += pic_cpu.o

hw/microblaze/petalogix_ml605_mmu.c

+3 −6
Original line number Diff line number Diff line
@@ -39,7 +39,6 @@ 
#include "hw/ssi.h"



#include "boot.h"

#include "pic_cpu.h"



#include "hw/stream.h"
@@ -82,20 +81,18 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) 
    Object *ds, *cs;

    MicroBlazeCPU *cpu;

    SysBusDevice *busdev;

    CPUMBState *env;

    DriveInfo *dinfo;

    int i;

    hwaddr ddr_base = MEMORY_BASEADDR;

    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);

    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

    qemu_irq irq[32], *cpu_irq;

    qemu_irq irq[32];



    /* init CPUs */

    if (cpu_model == NULL) {

        cpu_model = "microblaze";

    }

    cpu = cpu_mb_init(cpu_model);

    env = &cpu->env;



    /* Attach emulated BRAM through the LMB.  */

    memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
@@ -117,8 +114,8 @@ petalogix_ml605_init(QEMUMachineInitArgs *args) 
                          2, 0x89, 0x18, 0x0000, 0x0, 0);





    cpu_irq = microblaze_pic_init_cpu(env);

    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4);

    dev = xilinx_intc_create(INTC_BASEADDR, qdev_get_gpio_in(DEVICE(cpu),

                             MB_CPU_IRQ), 4);

    for (i = 0; i < 32; i++) {

        irq[i] = qdev_get_gpio_in(dev, i);

    }

hw/microblaze/petalogix_s3adsp1800_mmu.c

+3 −6
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#include "exec/address-spaces.h"



#include "boot.h"

#include "pic_cpu.h"



#define LMB_BRAM_SIZE  (128 * 1024)

#define FLASH_SIZE     (16 * 1024 * 1024)
@@ -63,13 +62,12 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) 
    const char *cpu_model = args->cpu_model;

    DeviceState *dev;

    MicroBlazeCPU *cpu;

    CPUMBState *env;

    DriveInfo *dinfo;

    int i;

    hwaddr ddr_base = MEMORY_BASEADDR;

    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);

    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);

    qemu_irq irq[32], *cpu_irq;

    qemu_irq irq[32];

    MemoryRegion *sysmem = get_system_memory();



    /* init CPUs */
@@ -77,7 +75,6 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) 
        cpu_model = "microblaze";

    }

    cpu = cpu_mb_init(cpu_model);

    env = &cpu->env;



    /* Attach emulated BRAM through the LMB.  */

    memory_region_init_ram(phys_lmb_bram, NULL,
@@ -96,8 +93,8 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) 
                          FLASH_SIZE >> 16,

                          1, 0x89, 0x18, 0x0000, 0x0, 1);



    cpu_irq = microblaze_pic_init_cpu(env);

    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 0xA);

    dev = xilinx_intc_create(INTC_BASEADDR, qdev_get_gpio_in(DEVICE(cpu),

                             MB_CPU_IRQ), 0xA);

    for (i = 0; i < 32; i++) {

        irq[i] = qdev_get_gpio_in(dev, i);

    }

hw/microblaze/pic_cpu.c

deleted100644 → 0
+0 −47
Original line number Diff line number Diff line 
/*

 * QEMU MicroBlaze CPU interrupt wrapper logic.

 *

 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "hw/hw.h"

#include "pic_cpu.h"



#define D(x)



static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)

{

    MicroBlazeCPU *cpu = opaque;

    CPUState *cs = CPU(cpu);

    int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;



    if (level) {

        cpu_interrupt(cs, type);

    } else {

        cpu_reset_interrupt(cs, type);

    }

}



qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)

{

    return qemu_allocate_irqs(microblaze_pic_cpu_handler, mb_env_get_cpu(env),

                              2);

}

hw/microblaze/pic_cpu.h

deleted100644 → 0
+0 −8
Original line number Diff line number Diff line 
#ifndef MICROBLAZE_PIC_CPU_H

#define MICROBLAZE_PIC_CPU_H



#include "qemu-common.h"



qemu_irq *microblaze_pic_init_cpu(CPUMBState *env);



#endif /*  MICROBLAZE_PIC_CPU_H */