Commit 71375b59 authored by Aleksandar Markovic's avatar Aleksandar Markovic
Browse files

target/mips: Style improvements in translate.c 



Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: default avatarAleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1566216496-17375-12-git-send-email-aleksandar.markovic@rt-rk.com>
parent eca3cbb8

target/mips/translate.c

+393 −380
Original line number Diff line number Diff line
@@ -170,7 +170,7 @@ enum { 
};









/* MIPS special opcodes */









#define MASK_SPECIAL(op)   MASK_OP_MAJOR(op) | (op & 0x3F)









#define MASK_SPECIAL(op)            (MASK_OP_MAJOR(op) | (op & 0x3F))

















enum {









    /* Shifts */








@@ -295,7 +295,7 @@ enum {







};

















/* Multiplication variants of the vr54xx. */









#define MASK_MUL_VR54XX(op)   MASK_SPECIAL(op) | (op & (0x1F << 6))









#define MASK_MUL_VR54XX(op)         (MASK_SPECIAL(op) | (op & (0x1F << 6)))

















enum {









    OPC_VR54XX_MULS    = (0x03 << 6) | OPC_MULT,








@@ -315,7 +315,7 @@ enum {







};

















/* REGIMM (rt field) opcodes */









#define MASK_REGIMM(op)    MASK_OP_MAJOR(op) | (op & (0x1F << 16))









#define MASK_REGIMM(op)             (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))

















enum {









    OPC_BLTZ     = (0x00 << 16) | OPC_REGIMM,








@@ -340,7 +340,7 @@ enum {







};

















/* Special2 opcodes */









#define MASK_SPECIAL2(op)  MASK_OP_MAJOR(op) | (op & 0x3F)









#define MASK_SPECIAL2(op)           (MASK_OP_MAJOR(op) | (op & 0x3F))

















enum {









    /* Multiply & xxx operations */








@@ -372,7 +372,7 @@ enum {







};

















/* Special3 opcodes */









#define MASK_SPECIAL3(op)  MASK_OP_MAJOR(op) | (op & 0x3F)









#define MASK_SPECIAL3(op)           (MASK_OP_MAJOR(op) | (op & 0x3F))

















enum {









    OPC_EXT      = 0x00 | OPC_SPECIAL3,








@@ -460,7 +460,7 @@ enum {







};

















/* BSHFL opcodes */









#define MASK_BSHFL(op)     MASK_SPECIAL3(op) | (op & (0x1F << 6))









#define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))

















enum {









    OPC_WSBH      = (0x02 << 6) | OPC_BSHFL,








@@ -474,7 +474,7 @@ enum {







};

















/* DBSHFL opcodes */









#define MASK_DBSHFL(op)    MASK_SPECIAL3(op) | (op & (0x1F << 6))









#define MASK_DBSHFL(op)             (MASK_SPECIAL3(op) | (op & (0x1F << 6)))

















enum {









    OPC_DSBH       = (0x02 << 6) | OPC_DBSHFL,








@@ -898,7 +898,7 @@ enum {







};

















/* Coprocessor 0 (rs field) */









#define MASK_CP0(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))









#define MASK_CP0(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))

















enum {









    OPC_MFC0     = (0x00 << 21) | OPC_CP0,








@@ -931,7 +931,7 @@ enum {







};

















/* MFMC0 opcodes */









#define MASK_MFMC0(op)     MASK_CP0(op) | (op & 0xFFFF)









#define MASK_MFMC0(op)              (MASK_CP0(op) | (op & 0xFFFF))

















enum {









    OPC_DMT      = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,








@@ -945,7 +945,7 @@ enum {







};

















/* Coprocessor 0 (with rs == C0) */









#define MASK_C0(op)        MASK_CP0(op) | (op & 0x3F)









#define MASK_C0(op)                 (MASK_CP0(op) | (op & 0x3F))

















enum {









    OPC_TLBR     = 0x01 | OPC_C0,








@@ -961,7 +961,7 @@ enum {







};

















/* Coprocessor 1 (rs field) */









#define MASK_CP1(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))









#define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))

















/* Values for the fmt field in FP instructions */









enum {








@@ -1009,8 +1009,8 @@ enum {







    OPC_BNZ_D    = (0x1F << 21) | OPC_CP1,









};

















#define MASK_CP1_FUNC(op)       MASK_CP1(op) | (op & 0x3F)









#define MASK_BC1(op)            MASK_CP1(op) | (op & (0x3 << 16))









#define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))









#define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))

















enum {









    OPC_BC1F     = (0x00 << 16) | OPC_BC1,








@@ -1029,7 +1029,7 @@ enum {







    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,









};

















#define MASK_CP2(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))









#define MASK_CP2(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))

















enum {









    OPC_MFC2    = (0x00 << 21) | OPC_CP2,








@@ -1142,7 +1142,7 @@ enum {







};

























#define MASK_CP3(op)       MASK_OP_MAJOR(op) | (op & 0x3F)









#define MASK_CP3(op)                (MASK_OP_MAJOR(op) | (op & 0x3F))

















enum {









    OPC_LWXC1       = 0x00 | OPC_CP3,








@@ -4227,7 +4227,10 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,







            tcg_temp_free(t2);









            tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);









            tcg_temp_free(t1);









            /* operands of different sign, first operand and result different sign */









            /*









             * Operands of different sign, first operand and result different









             * sign.









             */









            generate_exception(ctx, EXCP_OVERFLOW);









            gen_set_label(l1);









            gen_store_gpr(t0, rd);








@@ -9897,7 +9900,8 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,







        default:









            gen_mfc0(ctx, t0, rt, sel);









        }









    } else switch (sel) {









    } else {









        switch (sel) {









        /* GPR registers. */









        case 0:









            gen_helper_1e0i(mftgpr, t0, rt);








@@ -9976,6 +9980,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,







        default:









            goto die;









        }









    }









    trace_mips_translate_tr("mftr", rt, u, sel, h);









    gen_store_gpr(t0, rd);









    tcg_temp_free(t0);








@@ -10099,7 +10104,8 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,







        default:









            gen_mtc0(ctx, t0, rd, sel);









        }









    } else switch (sel) {









    } else {









        switch (sel) {









        /* GPR registers. */









        case 0:









            gen_helper_0e1i(mttgpr, t0, rd);








@@ -10185,6 +10191,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,







        default:









            goto die;









        }









    }









    trace_mips_translate_tr("mttr", rd, u, sel, h);









    tcg_temp_free(t0);









    return;








@@ -15669,7 +15676,10 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)







                save_cpu_state(ctx, 1);









                gen_helper_di(t0, cpu_env);









                gen_store_gpr(t0, rs);









                /* Stop translation as we may have switched the execution mode */









                /*









                 * Stop translation as we may have switched the execution









                 * mode.









                 */









                ctx->base.is_jmp = DISAS_STOP;









                tcg_temp_free(t0);









            }








@@ -15791,9 +15801,9 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)







    int extension = (ctx->opcode >> 6) & 0x3ff;









    uint32_t mips32_op;

















#define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc









#define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc









#define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc









#define FLOAT_1BIT_FMT(opc, fmt)    ((fmt << 8) | opc)









#define FLOAT_2BIT_FMT(opc, fmt)    ((fmt << 7) | opc)









#define COND_FLOAT_MOV(opc, cond)   ((cond << 7) | opc)

















    switch (extension) {









    case FLOAT_1BIT_FMT(CFC1, 0):








@@ -30190,7 +30200,8 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)







        }









    }

















    qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",









    qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x"









                 TARGET_FMT_lx "\n",









                 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);









    qemu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%016"









                 PRIx64 "\n",








@@ -30211,7 +30222,8 @@ void mips_tcg_init(void)







    cpu_gpr[0] = NULL;









    for (i = 1; i < 32; i++)









        cpu_gpr[i] = tcg_global_mem_new(cpu_env,









                                        offsetof(CPUMIPSState, active_tc.gpr[i]),









                                        offsetof(CPUMIPSState,









                                                 active_tc.gpr[i]),









                                        regnames[i]);

















    for (i = 0; i < 32; i++) {








@@ -30239,7 +30251,8 @@ void mips_tcg_init(void)







                                       regnames_LO[i]);









    }









    cpu_dspctrl = tcg_global_mem_new(cpu_env,









                                     offsetof(CPUMIPSState, active_tc.DSPControl),









                                     offsetof(CPUMIPSState,









                                              active_tc.DSPControl),









                                     "DSPControl");









    bcond = tcg_global_mem_new(cpu_env,









                               offsetof(CPUMIPSState, bcond), "bcond");