Commit 7097312d authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/ppc: Update vector support for v2.07 FP 



These new instructions are conditional on MSR.FP when TX=0 and
MSR.VEC when TX=1.  Since we only care about the Altivec registers,
and force TX=1, we can consider these to be Altivec instructions.
Since Altivec is true for any use of vector types, we only need
test have_isa_2_07.

This includes moves to and from the integer registers.

Tested-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent b2dda640

tcg/ppc/tcg-target.inc.c

+26 −6
Original line number Diff line number Diff line
@@ -586,6 +586,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, 
#define XXPERMDI   (OPCD(60) | (10 << 3) | 7)  /* v2.06, force ax=bx=tx=1 */

#define XXSEL      (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */



#define MFVSRD     (XO31(51) | 1)   /* v2.07, force sx=1 */

#define MFVSRWZ    (XO31(115) | 1)  /* v2.07, force sx=1 */

#define MTVSRD     (XO31(179) | 1)  /* v2.07, force tx=1 */

#define MTVSRWZ    (XO31(243) | 1)  /* v2.07, force tx=1 */



#define RT(r) ((r)<<21)

#define RS(r) ((r)<<21)

#define RA(r) ((r)<<16)
@@ -715,13 +720,28 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 
        tcg_debug_assert(TCG_TARGET_REG_BITS == 64);

        /* fallthru */

    case TCG_TYPE_I32:

        if (ret < TCG_REG_V0 && arg < TCG_REG_V0) {

        if (ret < TCG_REG_V0) {

            if (arg < TCG_REG_V0) {

                tcg_out32(s, OR | SAB(arg, ret, arg));

                break;

        } else if (ret < TCG_REG_V0 || arg < TCG_REG_V0) {

            /* Altivec does not support vector/integer moves.  */

            } else if (have_isa_2_07) {

                tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)

                          | VRT(arg) | RA(ret));

                break;

            } else {

                /* Altivec does not support vector->integer moves.  */

                return false;

            }

        } else if (arg < TCG_REG_V0) {

            if (have_isa_2_07) {

                tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)

                          | VRT(ret) | RA(arg));

                break;

            } else {

                /* Altivec does not support integer->vector moves.  */

                return false;

            }

        }

        /* fallthru */

    case TCG_TYPE_V64:

    case TCG_TYPE_V128: