Unverified Commit 6fce529c authored by Michael Clark's avatar Michael Clark
Browse files

RISC-V: Add mcycle/minstret support for -icount auto 



Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instructions will return the instruction count.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 8c59f5c1

target/riscv/op_helper.c

+26 −2
Original line number Diff line number Diff line
@@ -434,25 +434,49 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) 
    case CSR_INSTRET:

    case CSR_CYCLE:

        if (ctr_ok) {

#if !defined(CONFIG_USER_ONLY)

            if (use_icount) {

                return cpu_get_icount();

            } else {

                return cpu_get_host_ticks();

            }

#else

            return cpu_get_host_ticks();

#endif

        }

        break;

#if defined(TARGET_RISCV32)

    case CSR_INSTRETH:

    case CSR_CYCLEH:

        if (ctr_ok) {

#if !defined(CONFIG_USER_ONLY)

            if (use_icount) {

                return cpu_get_icount() >> 32;

            } else {

                return cpu_get_host_ticks() >> 32;

            }

#else

            return cpu_get_host_ticks() >> 32;

#endif

        }

        break;

#endif

#ifndef CONFIG_USER_ONLY

    case CSR_MINSTRET:

    case CSR_MCYCLE:

        if (use_icount) {

            return cpu_get_icount();

        } else {

            return cpu_get_host_ticks();

        }

    case CSR_MINSTRETH:

    case CSR_MCYCLEH:

#if defined(TARGET_RISCV32)

        if (use_icount) {

            return cpu_get_icount() >> 32;

        } else {

            return cpu_get_host_ticks() >> 32;

        }

#endif

        break;

    case CSR_MUCOUNTEREN:

target/riscv/translate.c

+2 −0
Original line number Diff line number Diff line
@@ -1390,6 +1390,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, 
        break;

    default:

        tcg_gen_movi_tl(imm_rs1, rs1);

        gen_io_start();

        switch (opc) {

        case OPC_RISC_CSRRW:

            gen_helper_csrrw(dest, cpu_env, source1, csr_store);
@@ -1413,6 +1414,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, 
            gen_exception_illegal(ctx);

            return;

        }

        gen_io_end();

        gen_set_gpr(rd, dest);

        /* end tb since we may be changing priv modes, to get mmu_index right */

        tcg_gen_movi_tl(cpu_pc, ctx->next_pc);