Commit 6fad9e98 authored by Alistair Francis's avatar Alistair Francis Committed by Edgar E. Iglesias
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target-microblaze: Convert pvr-full to a CPU property 



Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.

Signed-off-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 72e38754

target-microblaze/cpu-qom.h

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU { 
        bool dcache_writeback;

        bool endi;

        char *version;

        uint8_t pvr;

    } cfg;



    CPUMBState env;

target-microblaze/cpu.c

+4 −3
Original line number Diff line number Diff line
@@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 


    qemu_init_vcpu(cs);



    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \

                       | PVR0_USE_BARREL_MASK \

    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \

                       | PVR0_USE_DIV_MASK \

                       | PVR0_USE_HW_MUL_MASK \

                       | PVR0_USE_EXC_MASK \
@@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |

                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |

                        (version_code << 16);

                        (version_code << 16) |

                        (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);



    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |

                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -228,6 +228,7 @@ static Property mb_properties[] = { 
                     false),

    DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),

    DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),

    DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),

    DEFINE_PROP_END_OF_LIST(),

};

target-microblaze/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -212,7 +212,9 @@ typedef struct CPUMBState CPUMBState; 
/* MSR Reset value PVR mask */

#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF





#define C_PVR_NONE                      0

#define C_PVR_BASIC                     1

#define C_PVR_FULL                      2



/* CPU flags.  */

target-microblaze/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 
    mmu_available = 0;

    if (cpu->cfg.use_mmu) {

        mmu_available = 1;

        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)

            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

        if ((cpu->cfg.pvr == C_PVR_FULL) &&

            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

            mmu_available = 0;

        }

    }