Commit 6f4e1405 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

hw/arm/virt: Enable MTE via a machine property 



Control this cpu feature via a machine property, much as we do
with secure=on, since both require specialized support in the
machine setup to be functional.

Default MTE to off, since this feature implies extra overhead.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 873ec69a

hw/arm/virt.c

+34 −5
Original line number Diff line number Diff line
@@ -1837,12 +1837,19 @@ static void machvirt_init(MachineState *machine) 
                                     OBJECT(secure_sysmem), &error_abort);

        }



        if (vms->mte) {

            /* Create the memory region only once, but link to all cpus. */

            if (!tag_sysmem) {

                /*

         * The cpu adds the property if and only if MemTag is supported.

                 * The property exists only if MemTag is supported.

                 * If it is, we must allocate the ram to back that up.

                 */

        if (object_property_find(cpuobj, "tag-memory", NULL)) {

            if (!tag_sysmem) {

                if (!object_property_find(cpuobj, "tag-memory", NULL)) {

                    error_report("MTE requested, but not supported "

                                 "by the guest CPU");

                    exit(1);

                }



                tag_sysmem = g_new(MemoryRegion, 1);

                memory_region_init(tag_sysmem, OBJECT(machine),

                                   "tag-memory", UINT64_MAX / 32);
@@ -2061,6 +2068,20 @@ static void virt_set_ras(Object *obj, bool value, Error **errp) 
    vms->ras = value;

}



static bool virt_get_mte(Object *obj, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);



    return vms->mte;

}



static void virt_set_mte(Object *obj, bool value, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);



    vms->mte = value;

}



static char *virt_get_gic_version(Object *obj, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -2481,6 +2502,14 @@ static void virt_instance_init(Object *obj) 
                                    "Set on/off to enable/disable reporting host memory errors "

                                    "to a KVM guest using ACPI and guest external abort exceptions");



    /* MTE is disabled by default.  */

    vms->mte = false;

    object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);

    object_property_set_description(obj, "mte",

                                    "Set on/off to enable/disable emulating a "

                                    "guest CPU which implements the ARM "

                                    "Memory Tagging Extension");



    vms->irqmap = a15irqmap;



    virt_flash_create(vms);

include/hw/arm/virt.h

+1 −0
Original line number Diff line number Diff line
@@ -140,6 +140,7 @@ typedef struct { 
    bool its;

    bool virt;

    bool ras;

    bool mte;

    OnOffAuto acpi;

    VirtGICType gic_version;

    VirtIOMMUType iommu;

target/arm/cpu.c

+11 −8
Original line number Diff line number Diff line
@@ -1698,6 +1698,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
        cpu->id_pfr1 &= ~0xf000;

    }



#ifndef CONFIG_USER_ONLY

    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {

        /*

         * Disable the MTE feature bits if we do not have tag-memory

         * provided by the machine.

         */

        cpu->isar.id_aa64pfr1 =

            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);

    }

#endif



    /* MPU can be configured out of a PMSA CPU either by setting has-mpu

     * to false or by setting pmsav7-dregion to 0.

     */
@@ -1787,14 +1798,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
            cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",

                                   cpu->secure_tag_memory);

        }

    } else if (cpu_isar_feature(aa64_mte, cpu)) {

        /*

         * Since there is no tag memory, we can't meaningfully support MTE

         * to its fullest.  To avoid problems later, when we would come to

         * use the tag memory, downgrade support to insns only.

         */

        cpu->isar.id_aa64pfr1 =

            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);

    }



    cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);

target/arm/cpu64.c

+3 −2
Original line number Diff line number Diff line
@@ -646,8 +646,9 @@ static void aarch64_max_initfn(Object *obj) 
        t = cpu->isar.id_aa64pfr1;

        t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);

        /*

         * Begin with full support for MTE; will be downgraded to MTE=1

         * during realize if the board provides no tag memory.

         * Begin with full support for MTE. This will be downgraded to MTE=0

         * during realize if the board provides no tag memory, much like

         * we do for EL2 with the virtualization=on property.

         */

        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);

        cpu->isar.id_aa64pfr1 = t;