Commit 6e2c4633 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170711' into staging 



target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

# gpg: Signature made Tue 11 Jul 2017 11:28:15 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170711:
  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
  ARM: KVM: Enable in-kernel timers with user space gic
  aspeed: Register all watchdogs
  hw/misc: Add Exynos4210 Pseudo Random Number Generator

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 31fe1c41 792dac30

accel/kvm/kvm-all.c

+5 −0
Original line number Diff line number Diff line
@@ -2274,6 +2274,11 @@ int kvm_has_intx_set_mask(void) 
    return kvm_state->intx_set_mask;

}



bool kvm_arm_supports_user_irq(void)

{

    return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);

}



#ifdef KVM_CAP_SET_GUEST_DEBUG

struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,

                                                 target_ulong pc)

accel/stubs/kvm-stub.c

+5 −0
Original line number Diff line number Diff line
@@ -155,4 +155,9 @@ void kvm_init_cpu_signals(CPUState *cpu) 
{

    abort();

}



bool kvm_arm_supports_user_irq(void)

{

    return false;

}

#endif

hw/arm/aspeed_soc.c

+17 −8
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ static const AspeedSoCInfo aspeed_socs[] = { 
        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

        .wdts_num     = 2,

    }, {

        .name         = "ast2400-a1",

        .cpu_model    = "arm926",
@@ -72,6 +73,7 @@ static const AspeedSoCInfo aspeed_socs[] = { 
        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

        .wdts_num     = 2,

    }, {

        .name         = "ast2400",

        .cpu_model    = "arm926",
@@ -82,6 +84,7 @@ static const AspeedSoCInfo aspeed_socs[] = { 
        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

        .wdts_num     = 2,

    }, {

        .name         = "ast2500-a1",

        .cpu_model    = "arm1176",
@@ -92,6 +95,7 @@ static const AspeedSoCInfo aspeed_socs[] = { 
        .spi_bases    = aspeed_soc_ast2500_spi_bases,

        .fmc_typename = "aspeed.smc.ast2500-fmc",

        .spi_typename = aspeed_soc_ast2500_typenames,

        .wdts_num     = 3,

    },

};
@@ -175,9 +179,11 @@ static void aspeed_soc_init(Object *obj) 
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),

                              "ram-size", &error_abort);



    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);

    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);

    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());

    for (i = 0; i < sc->info->wdts_num; i++) {

        object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);

        object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);

        qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());

    }



    object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);

    object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
@@ -300,12 +306,15 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);



    /* Watch dog */

    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);

    for (i = 0; i < sc->info->wdts_num; i++) {

        object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);

        if (err) {

            error_propagate(errp, err);

            return;

        }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,

                        ASPEED_SOC_WDT_BASE + i * 0x20);

    }



    /* Net */

    qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);

hw/arm/exynos4210.c

+4 −0
Original line number Diff line number Diff line
@@ -87,6 +87,9 @@ 
/* Clock controller SFR base address */

#define EXYNOS4210_CLK_BASE_ADDR            0x10030000



/* PRNG/HASH SFR base address */

#define EXYNOS4210_RNG_BASE_ADDR            0x10830400



/* Display controllers (FIMD) */

#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
@@ -305,6 +308,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) 
    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);



    sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);

    sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);



    /* PWM */

    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,

hw/intc/arm_gic.c

+7 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "qom/cpu.h"

#include "qemu/log.h"

#include "trace.h"

#include "sysemu/kvm.h"



/* #define DEBUG_GIC */
@@ -1412,6 +1413,12 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) 
        return;

    }



    if (kvm_enabled() && !kvm_arm_supports_user_irq()) {

        error_setg(errp, "KVM with user space irqchip only works when the "

                         "host kernel supports KVM_CAP_ARM_USER_IRQ");

        return;

    }



    /* This creates distributor and main CPU interface (s->cpuiomem[0]) */

    gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);