Commit 6d809e7d authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/xtensa/tags/20190122-xtensa' into staging 



target/xtensa: zero overhead loops rework/helpers split

- change xtensa zero overhead loops implementation to avoid invalidation
  of TBs corresponding to previous loop body when a new loop is
  encountered;
- extract helper function groups from op_helper.c and move them into
  separate source files: exc_helper.c (exception helpers), win_helper.c
  (windowed registers helpers), fpu_helper.c (floating point helpers),
  mmu_helper.c (memory management helpers) and dbg_helper.c (native debug
  helpers).

# gpg: Signature made Tue 22 Jan 2019 18:44:17 GMT
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190122-xtensa:
  target/xtensa: move non-HELPER functions to helper.c
  target/xtensa: drop dump_state helper
  target/xtensa: extract interrupt and exception helpers
  target/xtensa: extract debug helpers
  target/xtensa: extract MMU helpers
  target/xtensa: extract windowed registers helpers
  target/xtensa: extract FPU helpers
  target/xtensa: rework zero overhead loops implementation

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents f6b06fcc 9584116f

target/xtensa/Makefile.objs

+5 −0
Original line number Diff line number Diff line
@@ -7,4 +7,9 @@ obj-y += core-test_kc705_be.o 
obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o

obj-y += xtensa-isa.o

obj-y += translate.o op_helper.o helper.o cpu.o

obj-$(CONFIG_SOFTMMU) += dbg_helper.o

obj-y += exc_helper.o

obj-y += fpu_helper.o

obj-y += gdbstub.o

obj-$(CONFIG_SOFTMMU) += mmu_helper.o

obj-y += win_helper.o

target/xtensa/cpu.h

+32 −0
Original line number Diff line number Diff line
@@ -400,6 +400,7 @@ struct XtensaConfig { 
    int excm_level;

    int ndepc;

    unsigned inst_fetch_width;

    unsigned max_insn_size;

    uint32_t vecbase;

    uint32_t exception_vector[EXC_MAX];

    unsigned ninterrupt;
@@ -695,6 +696,11 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) 
#define XTENSA_TBFLAG_CALLINC_MASK 0x180000

#define XTENSA_TBFLAG_CALLINC_SHIFT 19



#define XTENSA_CSBASE_LEND_MASK 0x0000ffff

#define XTENSA_CSBASE_LEND_SHIFT 0

#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000

#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16



static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,

        target_ulong *cs_base, uint32_t *flags)

{
@@ -706,6 +712,32 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, 
    *flags |= xtensa_get_ring(env);

    if (env->sregs[PS] & PS_EXCM) {

        *flags |= XTENSA_TBFLAG_EXCM;

    } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {

        target_ulong lend_dist =

            env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));



        /*

         * 0 in the csbase_lend field means that there may not be a loopback

         * for any instruction that starts inside this page. Any other value

         * means that an instruction that ends at this offset from the page

         * start may loop back and will need loopback code to be generated.

         *

         * lend_dist is 0 when LEND points to the start of the page, but

         * no instruction that starts inside this page may end at offset 0,

         * so it's still correct.

         *

         * When an instruction ends at a page boundary it may only start in

         * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE

         * for the TB that contains this instruction.

         */

        if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {

            target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];



            *cs_base = lend_dist;

            if (lbeg_off < 256) {

                *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;

            }

        }

    }

    if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&

            (env->sregs[LITBASE] & 1)) {

target/xtensa/dbg_helper.c

0 → 100644
+129 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include "qemu/osdep.h"

#include "qemu/main-loop.h"

#include "cpu.h"

#include "exec/helper-proto.h"

#include "qemu/host-utils.h"

#include "exec/exec-all.h"

#include "exec/address-spaces.h"



static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)

{

    uint32_t paddr;

    uint32_t page_size;

    unsigned access;

    int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,

                                       &paddr, &page_size, &access);

    if (ret == 0) {

        tb_invalidate_phys_addr(&address_space_memory, paddr,

                                MEMTXATTRS_UNSPECIFIED);

    }

}



void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)

{

    uint32_t change = v ^ env->sregs[IBREAKENABLE];

    unsigned i;



    for (i = 0; i < env->config->nibreak; ++i) {

        if (change & (1 << i)) {

            tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);

        }

    }

    env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);

}



void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)

{

    if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {

        tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);

        tb_invalidate_virtual_addr(env, v);

    }

    env->sregs[IBREAKA + i] = v;

}



static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,

        uint32_t dbreakc)

{

    CPUState *cs = CPU(xtensa_env_get_cpu(env));

    int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;

    uint32_t mask = dbreakc | ~DBREAKC_MASK;



    if (env->cpu_watchpoint[i]) {

        cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);

    }

    if (dbreakc & DBREAKC_SB) {

        flags |= BP_MEM_WRITE;

    }

    if (dbreakc & DBREAKC_LB) {

        flags |= BP_MEM_READ;

    }

    /* contiguous mask after inversion is one less than some power of 2 */

    if ((~mask + 1) & ~mask) {

        qemu_log_mask(LOG_GUEST_ERROR,

                      "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);

        /* cut mask after the first zero bit */

        mask = 0xffffffff << (32 - clo32(mask));

    }

    if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,

                              flags, &env->cpu_watchpoint[i])) {

        env->cpu_watchpoint[i] = NULL;

        qemu_log_mask(LOG_GUEST_ERROR,

                      "Failed to set data breakpoint at 0x%08x/%d\n",

                      dbreaka & mask, ~mask + 1);

    }

}



void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)

{

    uint32_t dbreakc = env->sregs[DBREAKC + i];



    if ((dbreakc & DBREAKC_SB_LB) &&

        env->sregs[DBREAKA + i] != v) {

        set_dbreak(env, i, v, dbreakc);

    }

    env->sregs[DBREAKA + i] = v;

}



void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)

{

    if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {

        if (v & DBREAKC_SB_LB) {

            set_dbreak(env, i, env->sregs[DBREAKA + i], v);

        } else {

            if (env->cpu_watchpoint[i]) {

                CPUState *cs = CPU(xtensa_env_get_cpu(env));



                cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);

                env->cpu_watchpoint[i] = NULL;

            }

        }

    }

    env->sregs[DBREAKC + i] = v;

}

target/xtensa/exc_helper.c

0 → 100644
+258 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include "qemu/osdep.h"

#include "qemu/main-loop.h"

#include "cpu.h"

#include "exec/helper-proto.h"

#include "qemu/host-utils.h"

#include "exec/exec-all.h"



void HELPER(exception)(CPUXtensaState *env, uint32_t excp)

{

    CPUState *cs = CPU(xtensa_env_get_cpu(env));



    cs->exception_index = excp;

    if (excp == EXCP_YIELD) {

        env->yield_needed = 0;

    }

    if (excp == EXCP_DEBUG) {

        env->exception_taken = 0;

    }

    cpu_loop_exit(cs);

}



void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)

{

    uint32_t vector;



    env->pc = pc;

    if (env->sregs[PS] & PS_EXCM) {

        if (env->config->ndepc) {

            env->sregs[DEPC] = pc;

        } else {

            env->sregs[EPC1] = pc;

        }

        vector = EXC_DOUBLE;

    } else {

        env->sregs[EPC1] = pc;

        vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;

    }



    env->sregs[EXCCAUSE] = cause;

    env->sregs[PS] |= PS_EXCM;



    HELPER(exception)(env, vector);

}



void HELPER(exception_cause_vaddr)(CPUXtensaState *env,

                                   uint32_t pc, uint32_t cause, uint32_t vaddr)

{

    env->sregs[EXCVADDR] = vaddr;

    HELPER(exception_cause)(env, pc, cause);

}



void debug_exception_env(CPUXtensaState *env, uint32_t cause)

{

    if (xtensa_get_cintlevel(env) < env->config->debug_level) {

        HELPER(debug_exception)(env, env->pc, cause);

    }

}



void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)

{

    unsigned level = env->config->debug_level;



    env->pc = pc;

    env->sregs[DEBUGCAUSE] = cause;

    env->sregs[EPC1 + level - 1] = pc;

    env->sregs[EPS2 + level - 2] = env->sregs[PS];

    env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |

        (level << PS_INTLEVEL_SHIFT);

    HELPER(exception)(env, EXC_DEBUG);

}



#ifndef CONFIG_USER_ONLY



void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)

{

    CPUState *cpu;



    env->pc = pc;

    env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |

        (intlevel << PS_INTLEVEL_SHIFT);



    qemu_mutex_lock_iothread();

    check_interrupts(env);

    qemu_mutex_unlock_iothread();



    if (env->pending_irq_level) {

        cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));

        return;

    }



    cpu = CPU(xtensa_env_get_cpu(env));

    cpu->halted = 1;

    HELPER(exception)(env, EXCP_HLT);

}



void HELPER(check_interrupts)(CPUXtensaState *env)

{

    qemu_mutex_lock_iothread();

    check_interrupts(env);

    qemu_mutex_unlock_iothread();

}



static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)

{

    if (xtensa_option_enabled(env->config,

                              XTENSA_OPTION_RELOCATABLE_VECTOR)) {

        return vector - env->config->vecbase + env->sregs[VECBASE];

    } else {

        return vector;

    }

}



/*!

 * Handle penging IRQ.

 * For the high priority interrupt jump to the corresponding interrupt vector.

 * For the level-1 interrupt convert it to either user, kernel or double

 * exception with the 'level-1 interrupt' exception cause.

 */

static void handle_interrupt(CPUXtensaState *env)

{

    int level = env->pending_irq_level;



    if (level > xtensa_get_cintlevel(env) &&

        level <= env->config->nlevel &&

        (env->config->level_mask[level] &

         env->sregs[INTSET] &

         env->sregs[INTENABLE])) {

        CPUState *cs = CPU(xtensa_env_get_cpu(env));



        if (level > 1) {

            env->sregs[EPC1 + level - 1] = env->pc;

            env->sregs[EPS2 + level - 2] = env->sregs[PS];

            env->sregs[PS] =

                (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;

            env->pc = relocated_vector(env,

                                       env->config->interrupt_vector[level]);

        } else {

            env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;



            if (env->sregs[PS] & PS_EXCM) {

                if (env->config->ndepc) {

                    env->sregs[DEPC] = env->pc;

                } else {

                    env->sregs[EPC1] = env->pc;

                }

                cs->exception_index = EXC_DOUBLE;

            } else {

                env->sregs[EPC1] = env->pc;

                cs->exception_index =

                    (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;

            }

            env->sregs[PS] |= PS_EXCM;

        }

        env->exception_taken = 1;

    }

}



/* Called from cpu_handle_interrupt with BQL held */

void xtensa_cpu_do_interrupt(CPUState *cs)

{

    XtensaCPU *cpu = XTENSA_CPU(cs);

    CPUXtensaState *env = &cpu->env;



    if (cs->exception_index == EXC_IRQ) {

        qemu_log_mask(CPU_LOG_INT,

                      "%s(EXC_IRQ) level = %d, cintlevel = %d, "

                      "pc = %08x, a0 = %08x, ps = %08x, "

                      "intset = %08x, intenable = %08x, "

                      "ccount = %08x\n",

                      __func__, env->pending_irq_level,

                      xtensa_get_cintlevel(env),

                      env->pc, env->regs[0], env->sregs[PS],

                      env->sregs[INTSET], env->sregs[INTENABLE],

                      env->sregs[CCOUNT]);

        handle_interrupt(env);

    }



    switch (cs->exception_index) {

    case EXC_WINDOW_OVERFLOW4:

    case EXC_WINDOW_UNDERFLOW4:

    case EXC_WINDOW_OVERFLOW8:

    case EXC_WINDOW_UNDERFLOW8:

    case EXC_WINDOW_OVERFLOW12:

    case EXC_WINDOW_UNDERFLOW12:

    case EXC_KERNEL:

    case EXC_USER:

    case EXC_DOUBLE:

    case EXC_DEBUG:

        qemu_log_mask(CPU_LOG_INT, "%s(%d) "

                      "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",

                      __func__, cs->exception_index,

                      env->pc, env->regs[0], env->sregs[PS],

                      env->sregs[CCOUNT]);

        if (env->config->exception_vector[cs->exception_index]) {

            uint32_t vector;



            vector = env->config->exception_vector[cs->exception_index];

            env->pc = relocated_vector(env, vector);

            env->exception_taken = 1;

        } else {

            qemu_log_mask(CPU_LOG_INT,

                          "%s(pc = %08x) bad exception_index: %d\n",

                          __func__, env->pc, cs->exception_index);

        }

        break;



    case EXC_IRQ:

        break;



    default:

        qemu_log("%s(pc = %08x) unknown exception_index: %d\n",

                 __func__, env->pc, cs->exception_index);

        break;

    }

    check_interrupts(env);

}

#else

void xtensa_cpu_do_interrupt(CPUState *cs)

{

}

#endif



bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

{

    if (interrupt_request & CPU_INTERRUPT_HARD) {

        cs->exception_index = EXC_IRQ;

        xtensa_cpu_do_interrupt(cs);

        return true;

    }

    return false;

}

target/xtensa/fpu_helper.c

0 → 100644
+166 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#include "qemu/osdep.h"

#include "qemu/main-loop.h"

#include "cpu.h"

#include "exec/helper-proto.h"

#include "qemu/host-utils.h"

#include "exec/exec-all.h"

#include "fpu/softfloat.h"



void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)

{

    static const int rounding_mode[] = {

        float_round_nearest_even,

        float_round_to_zero,

        float_round_up,

        float_round_down,

    };



    env->uregs[FCR] = v & 0xfffff07f;

    set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);

}



float32 HELPER(abs_s)(float32 v)

{

    return float32_abs(v);

}



float32 HELPER(neg_s)(float32 v)

{

    return float32_chs(v);

}



float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)

{

    return float32_add(a, b, &env->fp_status);

}



float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)

{

    return float32_sub(a, b, &env->fp_status);

}



float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)

{

    return float32_mul(a, b, &env->fp_status);

}



float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)

{

    return float32_muladd(b, c, a, 0, &env->fp_status);

}



float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)

{

    return float32_muladd(b, c, a, float_muladd_negate_product,

                          &env->fp_status);

}



uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)

{

    float_status fp_status = {0};



    set_float_rounding_mode(rounding_mode, &fp_status);

    return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status);

}



uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)

{

    float_status fp_status = {0};

    float32 res;



    set_float_rounding_mode(rounding_mode, &fp_status);



    res = float32_scalbn(v, scale, &fp_status);



    if (float32_is_neg(v) && !float32_is_any_nan(v)) {

        return float32_to_int32(res, &fp_status);

    } else {

        return float32_to_uint32(res, &fp_status);

    }

}



float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)

{

    return float32_scalbn(int32_to_float32(v, &env->fp_status),

                          (int32_t)scale, &env->fp_status);

}



float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)

{

    return float32_scalbn(uint32_to_float32(v, &env->fp_status),

                          (int32_t)scale, &env->fp_status);

}



static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)

{

    if (v) {

        env->sregs[BR] |= br;

    } else {

        env->sregs[BR] &= ~br;

    }

}



void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);

}



void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);

}



void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    int v = float32_compare_quiet(a, b, &env->fp_status);

    set_br(env, v == float_relation_equal || v == float_relation_unordered, br);

}



void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);

}



void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    int v = float32_compare_quiet(a, b, &env->fp_status);

    set_br(env, v == float_relation_less || v == float_relation_unordered, br);

}



void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    set_br(env, float32_le_quiet(a, b, &env->fp_status), br);

}



void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)

{

    int v = float32_compare_quiet(a, b, &env->fp_status);

    set_br(env, v != float_relation_greater, br);

}