Commit 6c441e1d authored by Peter Xu's avatar Peter Xu Committed by Michael S. Tsirkin
Browse files

intel_iommu: convert dbg macros to trace for trans 



Another patch to convert the DPRINTF() stuffs. This patch focuses on the
address translation path and caching.

Signed-off-by: default avatarPeter Xu <peterx@redhat.com>
Reviewed-by: default avatarJason Wang <jasowang@redhat.com>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent bc535e59

hw/i386/intel_iommu.c

+24 −45
Original line number Diff line number Diff line
@@ -260,11 +260,9 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, 
    uint64_t *key = g_malloc(sizeof(*key));

    uint64_t gfn = vtd_get_iotlb_gfn(addr, level);



    VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " iova 0x%"PRIx64

                " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, slpte,

                domain_id);

    trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);

    if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {

        VTD_DPRINTF(CACHE, "iotlb exceeds size limit, forced to reset");

        trace_vtd_iotlb_reset("iotlb exceeds size limit");

        vtd_reset_iotlb(s);

    }
@@ -505,8 +503,7 @@ static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index, 


    addr = s->root + index * sizeof(*re);

    if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {

        VTD_DPRINTF(GENERAL, "error: fail to access root-entry at 0x%"PRIx64

                    " + %"PRIu8, s->root, index);

        trace_vtd_re_invalid(re->rsvd, re->val);

        re->val = 0;

        return -VTD_FR_ROOT_TABLE_INV;

    }
@@ -524,15 +521,10 @@ static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index, 
{

    dma_addr_t addr;



    if (!vtd_root_entry_present(root)) {

        VTD_DPRINTF(GENERAL, "error: root-entry is not present");

        return -VTD_FR_ROOT_ENTRY_P;

    }

    /* we have checked that root entry is present */

    addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);

    if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {

        VTD_DPRINTF(GENERAL, "error: fail to access context-entry at 0x%"PRIx64

                    " + %"PRIu8,

                    (uint64_t)(root->val & VTD_ROOT_ENTRY_CTP), index);

        trace_vtd_re_invalid(root->rsvd, root->val);

        return -VTD_FR_CONTEXT_TABLE_INV;

    }

    ce->lo = le64_to_cpu(ce->lo);
@@ -704,12 +696,11 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 
    }



    if (!vtd_root_entry_present(&re)) {

        VTD_DPRINTF(GENERAL, "error: root-entry #%"PRIu8 " is not present",

                    bus_num);

        /* Not error - it's okay we don't have root entry. */

        trace_vtd_re_not_present(bus_num);

        return -VTD_FR_ROOT_ENTRY_P;

    } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) {

        VTD_DPRINTF(GENERAL, "error: non-zero reserved field in root-entry "

                    "hi 0x%"PRIx64 " lo 0x%"PRIx64, re.rsvd, re.val);

        trace_vtd_re_invalid(re.rsvd, re.val);

        return -VTD_FR_ROOT_ENTRY_RSVD;

    }
@@ -719,22 +710,17 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 
    }



    if (!vtd_context_entry_present(ce)) {

        VTD_DPRINTF(GENERAL,

                    "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") "

                    "is not present", devfn, bus_num);

        /* Not error - it's okay we don't have context entry. */

        trace_vtd_ce_not_present(bus_num, devfn);

        return -VTD_FR_CONTEXT_ENTRY_P;

    } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||

               (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) {

        VTD_DPRINTF(GENERAL,

                    "error: non-zero reserved field in context-entry "

                    "hi 0x%"PRIx64 " lo 0x%"PRIx64, ce->hi, ce->lo);

        trace_vtd_ce_invalid(ce->hi, ce->lo);

        return -VTD_FR_CONTEXT_ENTRY_RSVD;

    }

    /* Check if the programming of context-entry is valid */

    if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) {

        VTD_DPRINTF(GENERAL, "error: unsupported Address Width value in "

                    "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,

                    ce->hi, ce->lo);

        trace_vtd_ce_invalid(ce->hi, ce->lo);

        return -VTD_FR_CONTEXT_ENTRY_INV;

    } else {

        switch (ce->lo & VTD_CONTEXT_ENTRY_TT) {
@@ -743,9 +729,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, 
        case VTD_CONTEXT_TT_DEV_IOTLB:

            break;

        default:

            VTD_DPRINTF(GENERAL, "error: unsupported Translation Type in "

                        "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,

                        ce->hi, ce->lo);

            trace_vtd_ce_invalid(ce->hi, ce->lo);

            return -VTD_FR_CONTEXT_ENTRY_INV;

        }

    }
@@ -825,9 +809,8 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 
    /* Try to fetch slpte form IOTLB */

    iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);

    if (iotlb_entry) {

        VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " iova 0x%"PRIx64

                    " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr,

                    iotlb_entry->slpte, iotlb_entry->domain_id);

        trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,

                                 iotlb_entry->domain_id);

        slpte = iotlb_entry->slpte;

        reads = iotlb_entry->read_flags;

        writes = iotlb_entry->write_flags;
@@ -836,10 +819,9 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 
    }

    /* Try to fetch context-entry from cache first */

    if (cc_entry->context_cache_gen == s->context_cache_gen) {

        VTD_DPRINTF(CACHE, "hit context-cache bus %d devfn %d "

                    "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 ")",

                    bus_num, devfn, cc_entry->context_entry.hi,

                    cc_entry->context_entry.lo, cc_entry->context_cache_gen);

        trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,

                               cc_entry->context_entry.lo,

                               cc_entry->context_cache_gen);

        ce = cc_entry->context_entry;

        is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;

    } else {
@@ -848,19 +830,16 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 
        if (ret_fr) {

            ret_fr = -ret_fr;

            if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {

                VTD_DPRINTF(FLOG, "fault processing is disabled for DMA "

                            "requests through this context-entry "

                            "(with FPD Set)");

                trace_vtd_fault_disabled();

            } else {

                vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);

            }

            return;

        }

        /* Update context-cache */

        VTD_DPRINTF(CACHE, "update context-cache bus %d devfn %d "

                    "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 "->%"PRIu32 ")",

                    bus_num, devfn, ce.hi, ce.lo,

                    cc_entry->context_cache_gen, s->context_cache_gen);

        trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,

                                  cc_entry->context_cache_gen,

                                  s->context_cache_gen);

        cc_entry->context_entry = ce;

        cc_entry->context_cache_gen = s->context_cache_gen;

    }
@@ -870,8 +849,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus, 
    if (ret_fr) {

        ret_fr = -ret_fr;

        if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {

            VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests "

                        "through this context-entry (with FPD Set)");

            trace_vtd_fault_disabled();

        } else {

            vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);

        }
@@ -1031,6 +1009,7 @@ static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) 


static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)

{

    trace_vtd_iotlb_reset("global invalidation recved");

    vtd_reset_iotlb(s);

}

hw/i386/trace-events

+10 −0
Original line number Diff line number Diff line
@@ -20,6 +20,16 @@ vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write 
vtd_inv_desc_wait_irq(const char *msg) "%s"

vtd_inv_desc_wait_invalid(uint64_t hi, uint64_t lo) "invalid wait desc hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"

vtd_re_invalid(uint64_t hi, uint64_t lo) "invalid root entry hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present"

vtd_ce_invalid(uint64_t hi, uint64_t lo) "invalid context entry hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16

vtd_iotlb_page_update(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page update sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16

vtd_iotlb_cc_hit(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen) "IOTLB context hit bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32

vtd_iotlb_cc_update(uint8_t bus, uint8_t devfn, uint64_t high, uint64_t low, uint32_t gen1, uint32_t gen2) "IOTLB context update bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32" -> gen %"PRIu32

vtd_iotlb_reset(const char *reason) "IOTLB reset (reason: %s)"

vtd_fault_disabled(void) "Fault processing disabled for context entry"



# hw/i386/amd_iommu.c

amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" +  offset 0x%"PRIx32