Commit 6b8acf25 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 



The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
parent d02a8698

target/arm/translate.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -9719,8 +9719,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw 
    int conds;

    int conds;

    int logic_cc;

    int logic_cc;





    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)

    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

          || arm_dc_feature(s, ARM_FEATURE_M))) {

        /* Thumb-1 cores may need to treat bl and blx as a pair of

        /* Thumb-1 cores may need to treat bl and blx as a pair of

           16-bit instructions to get correct prefetch abort behavior.  */

           16-bit instructions to get correct prefetch abort behavior.  */

        insn = insn_hw1;

        insn = insn_hw1;