Commit 6b2b2a70 authored by Joel Stanley's avatar Joel Stanley Committed by Peter Maydell
Browse files

hw: wdt_aspeed: Add AST2600 support 



The AST2600 has four watchdogs, and they each have a 0x40 of registers.

When running as part of an ast2600 system we must check a different
offset for the system reset control register in the SCU.

Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 20190925143248.10000-12-clg@kaod.org
[clg: - reworked model integration into new object class ]
Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 6112bd6d

hw/watchdog/wdt_aspeed.c

+29 −0
Original line number Diff line number Diff line
@@ -40,12 +40,14 @@ 
#define     WDT_DRIVE_TYPE_MASK         (0xFF << 24)

#define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)

#define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)

#define WDT_RESET_MASK1                 (0x1c / 4)



#define WDT_TIMEOUT_STATUS              (0x10 / 4)

#define WDT_TIMEOUT_CLEAR               (0x14 / 4)



#define WDT_RESTART_MAGIC               0x4755



#define AST2600_SCU_RESET_CONTROL1      (0x40 / 4)

#define SCU_RESET_CONTROL1              (0x04 / 4)

#define    SCU_RESET_SDRAM              BIT(0)
@@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) 
        return s->regs[WDT_CTRL];

    case WDT_RESET_WIDTH:

        return s->regs[WDT_RESET_WIDTH];

    case WDT_RESET_MASK1:

        return s->regs[WDT_RESET_MASK1];

    case WDT_TIMEOUT_STATUS:

    case WDT_TIMEOUT_CLEAR:

        qemu_log_mask(LOG_UNIMP,
@@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, 
        s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;

        break;



    case WDT_RESET_MASK1:

        /* TODO: implement */

        s->regs[WDT_RESET_MASK1] = data;

        break;



    case WDT_TIMEOUT_STATUS:

    case WDT_TIMEOUT_CLEAR:

        qemu_log_mask(LOG_UNIMP,
@@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info = { 
    .class_init = aspeed_2500_wdt_class_init,

};



static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);



    dc->desc = "ASPEED 2600 Watchdog Controller";

    awc->offset = 0x40;

    awc->ext_pulse_width_mask = 0xfffff; /* TODO */

    awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;

    awc->reset_pulse = aspeed_2500_wdt_reset_pulse;

}



static const TypeInfo aspeed_2600_wdt_info = {

    .name = TYPE_ASPEED_2600_WDT,

    .parent = TYPE_ASPEED_WDT,

    .instance_size = sizeof(AspeedWDTState),

    .class_init = aspeed_2600_wdt_class_init,

};



static void wdt_aspeed_register_types(void)

{

    watchdog_add_model(&model);

    type_register_static(&aspeed_wdt_info);

    type_register_static(&aspeed_2400_wdt_info);

    type_register_static(&aspeed_2500_wdt_info);

    type_register_static(&aspeed_2600_wdt_info);

}



type_init(wdt_aspeed_register_types)

include/hw/arm/aspeed_soc.h

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
#include "hw/sd/aspeed_sdhci.h"



#define ASPEED_SPIS_NUM  2

#define ASPEED_WDTS_NUM  3

#define ASPEED_WDTS_NUM  4

#define ASPEED_CPUS_NUM  2

#define ASPEED_MACS_NUM  2

include/hw/watchdog/wdt_aspeed.h

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
    OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)

#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"

#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"

#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"



#define ASPEED_WDT_REGS_MAX        (0x20 / 4)